Patents by Inventor Shuhei Mitani
Shuhei Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160133743Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: ApplicationFiled: January 14, 2016Publication date: May 12, 2016Applicant: ROHM CO., LTD.Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
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Patent number: 9257521Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: GrantFiled: January 21, 2015Date of Patent: February 9, 2016Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
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Publication number: 20150318372Abstract: A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage Vth can be suppressed.Type: ApplicationFiled: December 2, 2013Publication date: November 5, 2015Inventors: Heiji WATANABE, Takuji HOSOI, Takayoshi SHIMURA, Ryota NAKAMURA, Yuki NAKANO, Shuhei MITANI, Takashi NAKAMURA, Hirokazu ASAHARA
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Patent number: 9159846Abstract: A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer.Type: GrantFiled: December 8, 2011Date of Patent: October 13, 2015Assignee: ROHM CO., LTD.Inventors: Shuhei Mitani, Masatoshi Aketa
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Patent number: 9136378Abstract: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.Type: GrantFiled: September 15, 2011Date of Patent: September 15, 2015Assignee: ROHM CO., LTD.Inventors: Keiji Okumura, Mineo Miura, Katsuhisa Nagao, Shuhei Mitani
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Publication number: 20150144967Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: ApplicationFiled: January 21, 2015Publication date: May 28, 2015Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
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Patent number: 8969877Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: GrantFiled: January 7, 2014Date of Patent: March 3, 2015Assignee: Rohm Co., Ltd.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
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Publication number: 20150034971Abstract: [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. [ Solution Means] A semiconductor device 1 has an MIS structure including an SiC epitaxial layer 3, a gate insulating film 9 and a gate electrode 10 formed on the gate insulating film 9. A gate insulating film 9 includes a silicon oxide film in contact with the SiC epitaxial layer 3. In the MIS structure, an area density QM of positive mobile ions in the gate insulating film 9 is made no more than 1×1012 cm?2.Type: ApplicationFiled: February 22, 2013Publication date: February 5, 2015Inventors: Heiji Watanabe, Takayoshi Sshimura, Takuji Hosoi, Shuhei Mitani, Yuki Nakano, Ryota Nakamura, Takashi Nakamura
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Patent number: 8901571Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches.Type: GrantFiled: August 27, 2013Date of Patent: December 2, 2014Assignee: Rohm Co., Ltd.Inventors: Yuki Nakano, Shuhei Mitani, Mineo Miura
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Publication number: 20140138708Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.Type: ApplicationFiled: January 7, 2014Publication date: May 22, 2014Applicant: ROHM CO., LTD.Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
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Publication number: 20140054611Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches.Type: ApplicationFiled: August 27, 2013Publication date: February 27, 2014Applicant: ROHM CO., LTD.Inventors: Yuki NAKANO, Shuhei MITANI, Mineo MIURA
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Patent number: 8653533Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.Type: GrantFiled: September 2, 2010Date of Patent: February 18, 2014Assignee: Rohm Co., Ltd.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
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Patent number: 8546814Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film.Type: GrantFiled: March 23, 2010Date of Patent: October 1, 2013Assignee: Rohm Co., Ltd.Inventors: Yuki Nakano, Shuhei Mitani, Mineo Miura
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Publication number: 20130248981Abstract: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.Type: ApplicationFiled: September 15, 2011Publication date: September 26, 2013Applicant: ROHM CO., LTD.Inventors: Keiji Okumura, Mineo Miura, Katsuhisa Nagao, Shuhei Mitani
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Publication number: 20120223338Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.Type: ApplicationFiled: September 2, 2010Publication date: September 6, 2012Applicant: Rohm Co. Ltd.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
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Publication number: 20120146055Abstract: A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer.Type: ApplicationFiled: December 8, 2011Publication date: June 14, 2012Applicant: ROHM CO., LTD.Inventors: Shuhei MITANI, Masatoshi Aketa
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Publication number: 20120012861Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film.Type: ApplicationFiled: March 23, 2010Publication date: January 19, 2012Applicant: ROHM CO., LTD.Inventors: Yuki Nakano, Shuhei Mitani, Mineo Miura
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Publication number: 20110012132Abstract: Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer 1 which is stacked on a surface of the n+-type substrate 11 containing SiC; n+-type source regions 5 arranged away from each other in a surface layer of the epitaxial layer 1; a p-type well contact region 2 sandwiched by the source regions 5; a p-type well region 3 arranged in contact with surfaces of the source regions 5 and p-type well contact region 2 on the substrate 11 side; and p-type well extension regions 4 arranged to sandwich the source regions 5 and p-type well region 3. The impurity concentration of the p-type well region 3 has a peak concentration at a position deeper in the depth direction from the surface of the epitaxial layer 1 toward the substrate 11 than the position of a peak concentration of the p-type well extension regions 4.Type: ApplicationFiled: February 6, 2009Publication date: January 20, 2011Applicant: Rohm Co., Ltd.Inventors: Takukazu Otsuka, Shuhei Mitani