Patents by Inventor Shui Liu

Shui Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067057
    Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing having an opening on a wall of the housing; a load port outside the housing; a robot arm inside the housing; and a processor. The load port is coupled to the wall and configured to load a wafer carrier for inspection. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.
    Type: Application
    Filed: April 27, 2018
    Publication date: February 28, 2019
    Inventors: Cheng-Kang Hu, Shau-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
  • Publication number: 20190067040
    Abstract: An apparatus for handling wafer carriers in a semiconductor fabrication facility (FAB) is disclosed. In one example, the apparatus includes: a table configured to receive a wafer carrier having a first door and operable to hold a plurality of wafers; an opening mechanism configured to open the first door of the wafer carrier; and a door storage space configured to store the first door. The apparatus may be either located on a floor of the FAB or physically coupled to a ceiling of the FAB.
    Type: Application
    Filed: January 30, 2018
    Publication date: February 28, 2019
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Alan Yang, Vic Huang, Hsu-Shui Liu, Jiun-Rong Pai
  • Publication number: 20190051546
    Abstract: The present disclosure relates to a method of automatically re-programming an EFEM to account for positional changes of the EFEM robot. In some embodiments, the method is performed by determining an initial position of an EFEM robot within an EFEM chamber. The EFEM robot at the initial position moves along a first plurality of steps defined relative to the initial position and that extend along a path between a first position and a second position. Positional parameters are determined, which describe a change between an initial position and a new position of the EFEM robot that is different than the initial position. A second plurality of steps are determined based upon the positional parameters. The EFEM robot at the new position moves along the second plurality of steps defined relative to the new position and that extend along the path between the first position and the second position.
    Type: Application
    Filed: November 27, 2017
    Publication date: February 14, 2019
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Publication number: 20190035696
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 31, 2019
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20190007074
    Abstract: A terminal includes a first baseband processor, a second baseband processor, a first radio frequency chip, a second radio frequency chip, a first antenna, a second antenna, a third antenna, and a fourth antenna. The first baseband processor is coupled to the first antenna and the second antenna using the first radio frequency chip. The first radio frequency chip is coupled to the first antenna to form a first channel, and is coupled to the second antenna to form a second channel. The second baseband processor is coupled to the third antenna and the fourth antenna using the second radio frequency chip. The second radio frequency chip is coupled to the third antenna to form a third channel, and is coupled to the fourth antenna to form a fourth channel.
    Type: Application
    Filed: July 27, 2016
    Publication date: January 3, 2019
    Inventors: Li Shen, Bangshi Yin, Kun Li, Songping Yao, Anmin Xu, Shumin Liu, Shui Liu
  • Patent number: 10170287
    Abstract: Some embodiments relate to a system. The system includes a radio frequency (RF) generator configured to output a RF signal. A transmission line is coupled to the RF generator. A plasma chamber is coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal. A micro-arc detecting element is configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Kuang Wu, Chih-Kuo Chang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sing-Tsung Li
  • Publication number: 20180366357
    Abstract: A system and method for inline detection of defects on a semiconductor wafer surface during a semiconductor device manufacturing process is disclosed herein. In one embodiment, a method includes: automatically transporting the wafer from a first processing station to an inspection station; scanning a wafer surface using a camera in the inspection station; generating at least one image of the wafer surface; analyzing the at least one image to detect defects on the wafer surface based on a set of predetermined criteria; if the wafer is determined to be defective, automatically transporting the wafer from the inspection station to a stocker; and if the wafer is determined to be not defective, automatically transporting the wafer to a second processing station for further processing in accordance with the semiconductor device manufacturing process.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 20, 2018
    Inventors: Chien-Ko LIAO, Hsu-Shui LIU, Jiun-Rong PAI, Sheng-Hsiang CHUANG, Shou-Wen KUO, Ya Hsun HSUEH
  • Patent number: 10020182
    Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The first and second sensors may communicate the parameters using different and incompatible protocols. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Shui Liu, Yeh-Chieh Wang, Jiun-Rong Pai, Pei-Nung Chen
  • Publication number: 20180151412
    Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.
    Type: Application
    Filed: February 22, 2017
    Publication date: May 31, 2018
    Inventors: Chun-Jung Huang, Hsu-Shui Liu, Han-Wen Liao, Yu-Yao Huang, Hsiao-Wei Chen, Yung-Lin Hsu, Kuang-Huan Hsu
  • Patent number: 9955397
    Abstract: A cell handover method and a terminal, where the method includes acquiring information about at least one candidate cell, performing priority sorting on the at least one candidate cell according to strength of interference to a received signal of a code division multiple access (CDMA) network of each candidate cell in the at least one candidate cell, sending a sorting result to a base station, receiving an indication message sent by the base station, where the indication message includes at least information about a target cell, performing a handover to the target cell according to the indication message, and hence interference to a received signal may be effectively prevented or reduced after a cell handover, communication quality and user experience are ensured, and additional network overheads and hardware design costs and complexity thereof are not increased.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 24, 2018
    Assignee: HUAWEI DEVICE (DONGGUAN) CO., LTD.
    Inventors: Xin Liu, Shui Liu, Zhenfeng Fan
  • Publication number: 20170372932
    Abstract: The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 28, 2017
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Pin-Yi Hsin, Shou-Wen Kuo, Patrick Lin
  • Patent number: 9852932
    Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mao-Lin Kao, Hsu-Shui Liu, Jiun-Rong Pai, Li-Jen Ko, Hsiang-Yin Shen, Tien-Chen Hu
  • Patent number: 9852936
    Abstract: A load port for a processing tool includes a carrier, a carrier actuator, an input table, an input table actuator, and a controller. The carrier has a plurality of cassette buffering spaces. The carrier is movable relative to the processing tool. The carrier actuator is operably connected to the carrier. The input table is configured to receive at least one cassette. The input table is movable relative to the carrier. The input table actuator is operably connected to the input table. The controller is configured to control the carrier actuator to move the carrier, such that one of the cassette buffering spaces is aligned with the input table, configured to control the input table actuator to move the input table with the cassette into the aligned cassette buffering space, and configured to control the input table to load the cassette into the aligned cassette buffering space.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 9786530
    Abstract: A wafer transfer method includes the following steps. An initial position of a first wafer in a wafer cassette is detected. A picking entry position in the wafer cassette is determined based on the initial position of the first wafer, in which the picking entry position is spaced apart from the initial position of the first wafer. A wafer transfer blade is moved to the picking entry position.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 9786539
    Abstract: A wafer chuck is provided. The wafer chuck includes a main body and a dielectric layer disposed over the main body. The wafer chuck also includes an electrode embedded in the dielectric layer and configured to generate an electrostatic field for retaining a wafer. The wafer chuck further includes a thermal conductive layer embedded in the main body or the dielectric layer. The thermal conductive layer has a lateral thermal conductivity greater than a vertical thermal conductivity.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yeh-Chieh Wang, Jiun-Rong Pai, Hsu-Shui Liu, Cheng-Lung Lee, Kuang-Chung Liou
  • Patent number: 9785989
    Abstract: Determining a characteristic group is disclosed, including: retrieving stored mapping relationship data for first objects and second objects, wherein the mapping relationship data describes connections between the first objects and the second objects; determining a candidate group including at least some of the first objects and at least some of the second objects based at least in part on the mapping relationship data, wherein any first object included in the candidate group is associated with another first object included in the candidate group via one or more other first object(s) or second object(s) included in the candidate group; determining a first characteristic value associated with the candidate group based at least in part on a number of first objects that are included in the candidate group; and determining whether the candidate group comprises a characteristic group based at least in part on the first characteristic value.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: October 10, 2017
    Assignee: Alibaba Group Holding Limited
    Inventors: Zhiqiang Chen, Haijie Gu, Jidong Shao, Guli Lin, Shui Liu
  • Patent number: 9741600
    Abstract: An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Hsieh, Chung-chieh Hsu, Chian-kun Chan, Chih-Kuo Chang, Chih-Ping Chen, Hsu-Shui Liu, Kai Lo, Wei-ting Hsiao, Yung-Kai Lin
  • Publication number: 20170148651
    Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 25, 2017
    Inventors: Mao-Lin KAO, Hsu-Shui LIU, Jiun-Rong PAI, Li-Jen KO, Hsiang-Yin SHEN, Tien-Chen HU
  • Patent number: 9558974
    Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: January 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Kao, Hsu-Shui Liu, Tien-Chen Hu, Li-Jen Ko, Hsiang-Yin Shen, Jiun-Rong Pai
  • Patent number: 9543181
    Abstract: A replaceable electrostatic chuck sidewall shield is provided. The replaceable electrostatic chuck sidewall shield fills or partially fills an indentation located between a base member and a top member of an electrostatic chuck, such that the replaceable electrostatic chuck sidewall shield may protect an epoxy in the indentation or may replace the epoxy within the indentation. The replaceable electrostatic chuck sidewall shield may be fully contained with the indentation. The replaceable electrostatic chuck sidewall shield may also cover an epoxy in the indentation such that the replaceable electrostatic chuck sidewall shield protrudes beyond the indentation. In an alternate embodiment, the replaceable electrostatic chuck sidewall shield substantially covers the area in which a conductive pole is embedded in a bipolar electrostatic chuck.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Shui Liu, Yeh-Chieh Wang, Jiun-Rong Pai