Patents by Inventor Shuichi Saito

Shuichi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7254923
    Abstract: A prefixed advertisement structure which is positioned mainly in downtown areas or places of heavy traffic, belonging to the field of advertisement making effective use of the wall surfaces of a building (1) conspicuous to passersby, etc. and which, in particular, is integrated with a glass sash wall (2) of a building (1). A prefixed advertisement structure integrated with a glass sash wall (2) of a building (1), wherein a advertising site is secured in advance on wall surface of the building in consideration of harmony with the external design of the building (1), providing a source of income from advertisement from the time of completion of the building (1) with an advertising medium attached in advance, and the advertisement structure harmonized with the external design of the building prevents the external appearance of the building (1) from being spoiled and attracts people's attention, thus proving increased advertising effects.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: August 14, 2007
    Assignee: Takenaka Corporation
    Inventors: Masahiro Hioki, Shuichi Saito, Mizuhiko Tamura, Kanji Matsushita
  • Patent number: 6928297
    Abstract: In a portable telephone including a plurality of input buttons 1 for inputting various indications, light emitting elements 7 which emit a light, when any one of the input buttons 1 is pushed on, diffusers 8 which are located under a plurality of input buttons 1 and which diffuse the light emitted from the light emitting element 7, the diffuser 8 has an incidence portion 5 which has a receiving plane positioned near the light emitting elements 7 and receiving the light emitted from the light emitting elements 7, and a projecting portion 6 which has a reflecting plane for reflecting the light received by the incidence portion 5 to an upper side of a plurality of input buttons 1.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: August 9, 2005
    Assignee: NEC Corporation
    Inventors: Hiromu Kitamura, Shuichi Saito
  • Patent number: 6887001
    Abstract: A key button switch structure for use in a handheld mobile phone, comprises an input button 1 having a push-down pressure transmitting projection A1 and a button inclination preventing projection B 3 both projected from a bottom surface of the input button, integrally with the input button. Two electrodes A9 and B 10 are formed on a substrate 8 fixed to a body casing 6. A dome-like switch contact 7 is provided to be pushed down by the push-down pressure transmitting projection A1 of the input button when the input button is depressed, thereby to electrically contact both the two electrodes.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 3, 2005
    Assignee: NEC Corporation
    Inventors: Hiromu Kitamura, Shuichi Saito
  • Patent number: 6799230
    Abstract: A control unit of a peripheral device enables data to be exchanged between a unit of the peripheral device and one of a plurality of higher-order devices by using one of a plurality of interface units. Thus, the unit of the peripheral device is controlled by the higher-order device corresponding to the used interface unit.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: September 28, 2004
    Assignee: Teac Corporation
    Inventors: Sho Sugiyama, Shuichi Saito, Yasuhide Ishimori
  • Publication number: 20040006929
    Abstract: A prefixed advertisement structure which is positioned mainly in downtown areas or places of heavy traffic, belonging to the field of advertisement making effective use of the wall surfaces of a building (1) conspicuous to passersby, etc. and which, in particular, is integrated with a glass sash wall (2) of a building (1). A prefixed advertisement structure integrated with a glass sash wall (2) of a building (1), wherein a advertising site is secured in advance on wall surface of the building in consideration of harmony with the external design of the building (1), providing a source of income from advertisement from the time of completion of the building (1) with an advertising medium attached in advance, and the advertisement structure harmonized with the external design of the building prevents the external appearance of the building (1) from being spoiled and attracts people's attention, thus proving increased advertising effects.
    Type: Application
    Filed: April 1, 2003
    Publication date: January 15, 2004
    Inventors: Masahiro Hioki, Shuichi Saito, Mizuhiko Tamura, Kanji Matsuhita
  • Patent number: 6670639
    Abstract: The present invention relates to a copper interconnection comprising a copper or copper alloy layer, wherein at least 50% of crystal grains of copper or a copper alloy form twins. A copper interconnection of the present invention is, therefore, highly reliable, and, a production cost thereof is low.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: December 30, 2003
    Assignee: NEC Corporation
    Inventors: Hidekazu Okabayashi, Akiko Fujii, Kazuyoshi Ueno, Shuichi Saito
  • Publication number: 20030034880
    Abstract: A control unit of a peripheral device enables data to be exchanged between a unit of the peripheral device and one of a plurality of higher-order devices by using one of a plurality of interface units. Thus, the unit of the peripheral device is controlled by the higher-order device corresponding to the used interface unit.
    Type: Application
    Filed: August 16, 2002
    Publication date: February 20, 2003
    Inventors: Sho Sugiyama, Shuichi Saito, Yasuhide Ishimori
  • Publication number: 20020167787
    Abstract: A key button switch structure for use in a handheld mobile phone, comprises an input button 1 having a push-down pressure transmitting projection A1 and a button inclination preventing projection B 3 both projected from a bottom surface of the input button, integrally with the input button. Two electrodes A9 and B 10 are formed on a substrate 8 fixed to a body casing 6. A dome-like switch contact 7 is provided to be pushed down by the push-down pressure transmitting projection A1 of the input button when the input button is depressed, thereby to electrically contact both the two electrodes.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 14, 2002
    Applicant: NEC CORPORATION
    Inventors: Hiromu Kitamura, Shuichi Saito
  • Patent number: 6444549
    Abstract: Upon fabrication of semiconductor devices, a semiconductor substrate is subjected to ion implantation with high energy. Subsequent annealing of the ion-implanted semiconductor substrate, when conducted by heating the substrate to a temperature of from 1,000° C. to 1,200° C. at a ramp-up rate of at least 200° C./sec, makes it possible to provide the resulting semiconductor devices with smaller leakage currents of reduced variations (&sgr;/X). The present invention can therefore provide a process for the fabrication of semiconductor devices featuring both smaller leakage currents and reduced variations of the leakage currents even when ion implantation is conducted with high energy.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: September 3, 2002
    Assignee: NEC Corporation
    Inventors: Toshiya Hayashi, Kouji Hamada, Naoharu Nishio, Kousuke Miyoshi, Shuichi Saito
  • Publication number: 20020094790
    Abstract: In a portable telephone including a plurality of input buttons 1 for inputting various indications, light emitting elements 7 which emit a light, when any one of the input buttons 1 is pushed on, diffusers 8 which are located under a plurality of input buttons 1 and which diffuse the light emitted from the light emitting element 7, the diffuser 8 has an incidence portion which has a receiving plane positioned near the light emitting elements 7 and receiving the light emitted from the light emitting elements 7, and a projecting portion 6 which has a reflecting plane for reflecting the light received by the incidence portion 5 to an upper side of a plurality of input buttons 1.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 18, 2002
    Applicant: NEC Corporation
    Inventors: Hiromu Kitamura, Shuichi Saito
  • Patent number: 6372591
    Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to form shallow extensions (e.g., 0.1 &mgr;m or less in depth) of source/drain regions of a MOSFET with a double drain structure. In the step (a), a gate electrode is formed over a main surface of a single-crystal Si substrate of a first conductivity type through a gate insulating film. In the step (b), a dopant of a second conductivity type is ion-implanted into the substrate at an acceleration energy of 1 keV or lower under a condition that the amount of point defects induced in this step (b) is minimized or decreased, thereby forming first and second doped regions of the second conductivity type. In the step (c), a pair of sidewalls spacers are formed.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Akira Mineji, Seiichi Shishiguchi, Shuichi Saito
  • Publication number: 20020009841
    Abstract: Upon fabrication of semiconductor devices, a semiconductor substrate is subjected to ion implantation with high energy. Subsequent annealing of the ion-implanted semiconductor substrate, when conducted by heating the substrate to a temperature of from 1,000° C. to 1,200° C. at a ramp-up rate of at least 200° C./sec, makes it possible to provide the resulting semiconductor devices with smaller leakage currents of reduced variations (&sgr;/X). The present invention can therefore provide a process for the fabrication of semiconductor devices featuring both smaller leakage currents and reduced variations of the leakage currents even when ion implantation is conducted with high energy.
    Type: Application
    Filed: September 1, 1998
    Publication date: January 24, 2002
    Inventors: TOSHIYA HAYASHI, KOUJI HAMADA, NAOHARU NISHIO, KOUSUKE MIYOSHI, SHUICHI SAITO
  • Publication number: 20010012670
    Abstract: A semiconductor device is manufactured by a step of forming a gate electrode on a semiconductor substrate with a gate insulation film therebetween, and using this gate electrode as a mask to implant ions to achieve a high-dose doping of impurities, thereby forming a source/drain region, using an accelerating potential for ion implantation that is lower to a value at which implantation damage is not done to the gate insulation film.
    Type: Application
    Filed: November 19, 1998
    Publication date: August 9, 2001
    Inventors: AKIRA MINEJI, SEIICHI SHISHIGUCHI, SHUICHI SAITO
  • Patent number: 6121137
    Abstract: The invention provides a method of fabricating a semiconductor device, including the steps of (a) depositing a titanium film over a silicon substrate, (b) depositing an amorphous silicon film on the titanium film, (c) carrying out first thermal annealing to form a first TiSi.sub.2 film over a resultant, (d) carrying out second thermal annealing to cause a single crystal silicon layer to grow in a region in which a source/drain region is to be formed, (e) successively removing the amorphous silicon film and the first TiSi.sub.2 film, and (f) forming a highly concentrated diffusion layer in the region, the diffusion layer having conductivity opposite to that of the silicon substrate. In accordance with the method, it is possible to form a salicided MOS transistor which includes a source/drain diffusion layer having shallow junction depth, and low-resistive source/drain regions.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventor: Shuichi Saito
  • Patent number: 6078365
    Abstract: An active matrix liquid crystal panel includes a plurality of thin film transistors respectively arranged adjacent to pixel electrodes, and a plurality of auxiliary capacitances. Each transistor has a semiconductor active layer, a pair of source and drain electrodes, and a gate electrode opposing the active layer via a gate insulating film. Each auxiliary capacitance has upper and lower electrodes, and a dielectric layer sandwiched between the upper and lower electrodes. The gate electrode, the lower electrode, and an address line respectively have portions formed of a common refractory metal film arranged on the insulating surface of a support substrate. The source and drain electrodes, the upper electrode, and a signal line respectively have portions formed of a common Mo film. Each pixel electrode has a portion formed of an ITO film. Each auxiliary capacitance further has an intervening layer between the dielectric layer and the upper electrode.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: June 20, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomomasa Ueda, Yutaka Onozuka, Yujiro Hara, Shuichi Saito, Mitsushi Ikeda
  • Patent number: 5920567
    Abstract: A router is connected to a network having a terminal and also connected to other routers via an ISDN, and inter-network routing information retained by each router is transferred through the ISDN. In response to a routing information request from the terminal, the router establishes a connection with another router by means of an ISDN address in its first table. Then, the router receives, learns and retains the routing information transmitted from the other router, thus making it unnecessary to set all required routing information, and then sends the routing information to the network connected thereto.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: July 6, 1999
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Shuichi Saito, Mikako Nanba, Makoto Nakamura
  • Patent number: 5837597
    Abstract: A method of manufacturing a semiconductor device in which a first ion implantation is carried out into a semiconductor substrate. Then, a second ion implantation is carried out to a projection range deeper than that of the first ion implantation. The ions of the second implantation are formed from the same type of atoms constituting the semiconductor substrate or from impurity atoms having the same conduction type as the semiconductor substrate at the projection range of the second ion implantation. A further ion implantation may be carried out to electrically shield the second implantation, or the method may be carried out in a SOI substrate with the second implantation extending through the insulating layer of the SOI structure.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: November 17, 1998
    Assignee: NEC Corporation
    Inventor: Shuichi Saito
  • Patent number: 5820921
    Abstract: A phosphor layer is formed on an inside surface of a panel of a glass bulb comprising the panel and funnel connected with each other. A nozzle sprays an organic solvent lacquer on the phosphor layer to form a lacquer intermediate film under conditions ofa/2.ltoreq.L.multidot.tan (.THETA./2).ltoreq.(a/2)+.alpha.(0.ltoreq..alpha. )where,a is the length of the short side of the inside surface of the panel,L is the length from the connecting portion of the panel and funnel to the nozzle in the direction of spray,.THETA.0 is the angle of spray of the nozzle, and.alpha. is a length addition parameter. The lacquer intermediate film formed on the inside surface of the funnel is removed by a liquid.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: October 13, 1998
    Assignee: Sony Corporation
    Inventors: Saori Kawase, Nobuyuki Matsushima, Shuichi Saito
  • Patent number: 5820920
    Abstract: A method of producing a cathode ray tube comprising forming a phosphor layer on the inner surface of a panel of a glass bulb, forming an lacquer intermediate film on the phosphor layer, removing the lacquer intermediate film formed on the inner surface of the funnel of the glass bulb by a liquid in a state with the temperature of the glass bulb higher than the temperature of the liquid.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: October 13, 1998
    Assignee: Sony Corporation
    Inventors: Saori Ariji, Nobuyuki Matsushima, Shuichi Saito
  • Patent number: 5759899
    Abstract: The invention provides a method of fabricating a semiconductor device, including the steps of (a) depositing a titanium film over a silicon substrate, (b) depositing an amorphous silicon film on the titanium film, (c) carrying out first thermal annealing to form a first TiSi.sub.2 film over a resultant, (d) carrying out second thermal annealing to cause a single crystal silicon layer to grow in a region in which a source/drain region is to be formed, (e) successively removing the amorphous silicon film and the first TiSi.sub.2 film, and (f) forming a highly concentrated diffusion layer in the region, the diffusion layer having conductivity opposite to that of the silicon substrate. In accordance with the method, it is possible to form a salicided MOS transistor which includes a source/drain diffusion layer having shallow junction depth, and low-resistive source/drain regions.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: June 2, 1998
    Assignee: NEC Corporation
    Inventor: Shuichi Saito