Patents by Inventor Shuji Miyasaka

Shuji Miyasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080225173
    Abstract: A signal processing apparatus capable of efficiently processing bitstream in a small circuit scale includes an input buffer in which a bitstream is stored, a first processor which generates a program for processing a signal B corresponding to a signal A by taking out the signal A from the bitstream stored in the input buffer and by using at least one related signal included in the signal A, the related signal being related to the signal B; and a second processor which acquires the program generated by the first processor and executes the acquired program to process the signal B corresponding to the signal A.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 18, 2008
    Inventors: Shuji Miyasaka, Yuji Sugisawa, Akihiro Kato, Futoshi Morie
  • Publication number: 20080168232
    Abstract: A cache memory according to the present invention includes: a W flag setting unit (40) that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order; and a replace unit (39) that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
    Type: Application
    Filed: November 2, 2004
    Publication date: July 10, 2008
    Inventors: Hazuki Okabayashi, Ryuta Nakanishi, Tetsuya Tanaka, Shuji Miyasaka
  • Publication number: 20080059203
    Abstract: Provided are an audio encoding device and an audio decoding device, by which optimal trade-off between code rates and sound quality can be flexibly adjusted. A variable frequency segmentation encoding unit (110) has: difference degree calculation units (101, 102, and 103) for calculating a difference degree between the first and second input signals, depending on a segmentation method A, B, or C for segmenting a frequency band into sub-bands; a selection unit (104) for selecting one of the segmentation methods; and a difference degree and segmentation information encoding unit (105) for encoding the selected method and the difference degree for each sub-band by the method.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 6, 2008
    Inventors: Mineo Tsushima, Yoshiaki Takagi, Kojiro Ono, Naoya Tanaka, Shuji Miyasaka
  • Publication number: 20070271095
    Abstract: An audio encoder, which is capable of encoding multiple-channel signals so that only a downmixed signal is decoded and of further generating specific auxiliary information necessary for dividing the downmixed signal, is provided. An audio encoder (10), which compresses and encodes audio signals of N-channels (N>1), includes a downmixed signal encoding unit (11) which encodes the downmixed signal obtained by downmixing the audio signals, and an auxiliary information generation unit (12a) which generates auxiliary information necessary for decoding the downmixed signal encoded by the downmixed signal encoding unit (11) into N-channel audio signals.
    Type: Application
    Filed: August 18, 2005
    Publication date: November 22, 2007
    Inventors: Shuji Miyasaka, Yoshiaki Takagi, Naoya Tanaka, Mineo Tsushima
  • Publication number: 20070255572
    Abstract: An audio decoder which reproduces original signals from a bit stream including a downmix signal of the original signals and supplementary information indicating the gain ratio D and the phase difference ? between the original signals.
    Type: Application
    Filed: August 2, 2005
    Publication date: November 1, 2007
    Inventors: Shuji Miyasaka, Yoshiaki Takagi, Naoya Tanaka, Mineo Tsushima
  • Publication number: 20070256065
    Abstract: An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
    Type: Application
    Filed: April 24, 2007
    Publication date: November 1, 2007
    Inventors: Taketo Heishi, Toshiyuki Sakata, Hajime Ogawa, Ryoko Miyachi, Shuji Miyasaka, Tomokazu Ishikawa
  • Patent number: 7284241
    Abstract: An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: October 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taketo Heishi, Toshiyuki Sakata, Hajime Ogawa, Ryoko Miyachi, Shuji Miyasaka, Tomokazu Ishikawa
  • Publication number: 20070239463
    Abstract: A decoding device (30a) comprises a narrow-band decoding unit (31) operable to reproduce a PCM signal (P1) from a narrow-band bit stream included in a wide-band bit stream (S0), a wide-band decoding unit (32) operable to reproduce a PCM signal (P2) having a frequency band which is wider than that of the PCM signal (P1) reproduced by the narrow-band decoding unit (31) from the narrow-band bit stream and a band expanding bit stream included in the wide band bit stream (S0) and a selecting unit (34) operable to select either the PCM signal (P1) reproduced by the narrow-band decoding unit (31) or the PCM signal (P2) reproduced by the wide-band decoding unit (32), and to output the selected sound digital signal.
    Type: Application
    Filed: June 5, 2007
    Publication date: October 11, 2007
    Inventors: Shuji Miyasaka, Tomokazu Ishikawa, Yoshiaki Sawada
  • Patent number: 7260540
    Abstract: A decoding device (30a) comprises a narrow-band decoding unit (31) operable to reproduce a PCM signal (P1) from a narrow-band bit stream included in a wide-band bit stream (S0), a wide-band decoding unit (32) operable to reproduce a PCM signal (P2) having a frequency band which is wider than that of the PCM signal (P1) reproduced by the narrow-band decoding unit (31) from the narrow-band bit stream and a band expanding bit stream included in the wide band bit stream (S0) and a selecting unit (34) operable to select either the PCM signal (P1) reproduced by the narrow-band decoding unit (31) or the PCM signal (P2) reproduced by the wide-band decoding unit (32), and to output the selected sound digital signal.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: August 21, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Miyasaka, Tomokazu Ishikawa, Yoshiaki Sawada
  • Publication number: 20070162278
    Abstract: An audio encoder, generating a stereo signal based on a multi-channel signal, includes a downmix unit (100) for downmixing a multi-channel signal exceeding two channels to a two-channel stereo signal, a first coding unit (101) for generating a first coded signal by coding the downmixed stereo signal, a second coding unit (102) for generating a second coded signal by coding information to restore the downmixed stereo signal to a multi-channel signal, a code size calculating unit (103) for calculating a code size of the second coded signal, and a first multiplexing unit (104) for multiplexing the calculated code size in either the first coded signal or the second coded signal. Accordingly a decoder is able to easily extract a coded signal of the multi-channel signal based on the code size, and the decoder reproducing only the downmixed signal can be configured inexpensively.
    Type: Application
    Filed: February 9, 2005
    Publication date: July 12, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shuji Miyasaka, Yoshiaki Takagi, Kazutaka Abe
  • Patent number: 7243061
    Abstract: With respect to audio signal coding and decoding apparatuses, there is provided a coding apparatus that enables a decoding apparatus to reproduce an audio signal even through it does not use all of data from the coding apparatus, and a decoding apparatus corresponding to the coding apparatus. A quantization unit constituting a coding apparatus includes a first sub-quantization unit comprising sub-quantization units for low-band, intermediate-band, and high-band; a second sub-quantization unit for quantizing quantization errors from the first sub-quantization unit; and a third sub-quantization unit for quantizing quantization errors which have been processed by the first sub-quantization unit and the second sub-quantization unit.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Norimatsu, Shuji Miyasaka, Yoshihisa Nakatoh, Mineo Tsushima, Tomokazu Ishikawa
  • Publication number: 20070143548
    Abstract: The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 21, 2007
    Inventors: Ryuta Nakanishi, Hazuki Okabayashi, Tetsuya Tanaka, Shuji Miyasaka
  • Patent number: 7188133
    Abstract: In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented by a*(2^n) where a mantissa is a and an exponent is n, the mantissa is stored as a fixed point number in the upper U bits of N-bit field (N?(U+L)) and the exponent is stored as an integer in the lower L bits. For the multiplication of two real numbers represented in such a format, these two real numbers are multiplied as fixed point numbers so as to make only the upper significant bits of the multiplication result a mantissa, while these two real numbers are added as integers so as to make only the lower significant bits of the addition result an exponent. As a result, the multiplication result can be obtained in a floating point format.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: March 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Miyasaka, Tomokazu Ishikawa
  • Patent number: 7185176
    Abstract: A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: February 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd,
    Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Yoshihiro Koga, Manabu Kuroda, Masato Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Shuji Miyasaka
  • Patent number: 7069223
    Abstract: An audio decoding device is provided for decoding NA (where NA>1) channels of audio signals by a sub-band synthesis operation using sub-band synthesis filter data and sub-band signal data. The decoding device includes a first memory section for storing MA (where MA<NA) channels of the sub-band synthesis filter data and the sub-band signal data, a second memory section for storing at least some of NA channels, an operation section for receiving encoded audio data and decoding the encoded audio data into sub-band signal data, and a data transfer section for, switching, by MA channels, the sub-band synthesis filter data and the sub-band signal data in the first memory section and the second memory section.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: June 27, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaharu Matsumoto, Takashi Katayama, Masahiro Sueyoshi, Shuji Miyasaka, Takeshi Fujita, Akihisa Kawamura, Tsukuru Ishito, Eiji Otomura, Tsuyoshi Nakamura
  • Patent number: 6999828
    Abstract: The present invention is a signal processing device which performs parallel processes A and B efficiently. There is a deviation in the throughputs of the process A and B in processing an audio signal. First to Nth sub signal processing sections have capabilities to complete the process A within a period (N×T). A main signal processing sections has a capability to complete the process B within a period T. Efficient signal processing can be achieved by processing an input digital signal by means of distinct sub signal processing devices one after another and then processing the signal by the main signal processing section. (N×T).
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Miyasaka, Takeshi Norimatsu, Mineo Tsushima, Tomokazu Ishikawa, Yoshiaki Sawada
  • Publication number: 20050182902
    Abstract: A signal processing apparatus (1) performs decoding using a first memory area (11) of a main memory (10), a first table (13) of a second memory area (12) and a second table (14). The signal processing apparatus (1) has a cache memory (34) for temporarily storing data of the first table (13) and the second table (14), a processor (20) which reads out the data by accessing at least one of the first memory area (11) and the second memory area (12) via the cache memory (34), and a control unit (51) which allocates a space in the cache memory (34) when there is no space for temporarily storing in the cache memory (34). The control unit (51) allocates the space in the cache memory (34) into which the data in the first memory area (11) is stored preferentially to the data in the second memory area (12).
    Type: Application
    Filed: February 9, 2005
    Publication date: August 18, 2005
    Inventor: Shuji Miyasaka
  • Patent number: 6917712
    Abstract: An encoding apparatus includes a quantized spectral sequence generation section for generating a quantized spectral sequence by quantizing an audio signal with a predetermined quantization precision, and a circulating code vector quantization section for outputting a spectral sequence code containing circulating position identification information indicating how much a reference spectral sequence is circulated to obtain a circulant quantized spectral sequence which is most similar to the quantized spectral sequence.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: July 12, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mineo Tsushima, Takeshi Norimatsu, Shuji Miyasaka, Tomokazu Ishikawa, Yoshiaki Sawada
  • Patent number: 6904404
    Abstract: With respect to audio signal coding and decoding apparatuses, there is provided a coding apparatus that enables a decoding apparatus to reproduce an audio signal even through it does not use all of data from the coding apparatus, and a decoding apparatus corresponding to the coding apparatus. A quantization unit constituting a coding apparatus includes a first sub-quantization unit comprising sub-quantization units for low-band, intermediate-band, and high-band; a second sub-quantization unit for quantizing quantization errors from the first sub-quantization unit; and a third sub-quantization unit for quantizing quantization errors which have been processed by the first sub-quantization unit and the second sub-quantization unit.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Norimatsu, Shuji Miyasaka, Yoshihisa Nakatoh, Mineo Tsushima, Tomokazu Ishikawa
  • Patent number: 6904089
    Abstract: An encoding device includes an encoding section for generating hit streams having a variable frame length from an input audio signal, a maximum frame length of the bit streams being fixed; a storage section for storing the bit streams generated by the encoding section; and a transfer section for transferring the bit streams at a prescribed transfer rate. The storage section includes a buffer having a capacity corresponding to at least a value which is obtained by subtracting an amount of the bit streams transferable in one frame time period at a minimum possible transfer rate from a value of twice the maximum frame length.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Sueyoshi, Masaharu Matsumoto, Kazutaka Abe, Kousuke Nishio, Takashi Katayama, Akihisa Kawamura, Shuji Miyasaka, Takeshi Fujita