Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

Abstract: In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.

Abstract: A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal.

Abstract: Provided is a shift register with which an increase in power consumption can be inhibited, and with which malfunctions due to electric potential Modification Example between gate terminals of output transistors can be inhibited, while inhibiting an increase in circuit size. A bistable circuit of a shift register is provided with first to fourth transistors. In the third transistor, a gate terminal thereof is connected to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to a second input terminal, and a second conduction terminal thereof is connected to an output terminal. In the fourth transistor, a gate terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the gate terminal of the third transistor and the output terminal.

Abstract: Provided is a shift register capable of being driven using various clock signals, with low power consumption. A bistable circuit of a shift register is provided with first to third transistors, first to third input terminals, and an output terminal. In the first transistor, a gate terminal thereof and a first conduction terminal thereof are connected to the first input terminal. In the second transistor, a gate terminal thereof is connected to the third input terminal, and a first conduction terminal thereof is connected to the first input terminal. In the third transistor, a gate terminal thereof is connected respectively to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the output terminal.

Abstract: An objective of the present invention is to provide a display device capable of suppressing consumption of the current flowing through gate clock signal bus lines by reducing the loads on the gate clock signal bus lines. In a shift register, which writes the voltages of a plurality of gate clock signals (CK1 to CK3) to gate bus lines (GL) via buffer circuits (BF), a plurality of gate clock signal bus lines (51a to 54a) are formed in an area between a display portion (600) and the buffer circuits (BF), independently of a clear signal bus line and other lines, so as to be adjacent to the buffer circuits (BF). This results in no area in which clear signal branch lines (61b) cross the gate clock signal bus lines (51a to 54a) and wiring lines in bistable circuits SR. Thus, it is possible to eliminate interlayer capacitance due to the crossings of the lines and fringe capacitance between the lines.

Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Abstract: In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.

Abstract: In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.

Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Abstract: A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

Abstract: A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14).

Abstract: In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (?Vcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.

Abstract: A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source for supplying a first potential level; a second power source for supplying a second potential level, a third power source for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

Abstract: Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.

Abstract: A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.

Abstract: An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between ?VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively.

Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Abstract: A plurality of display panels (10A and 10B) are provided on a single substrate (2). Data signal lines (11A), scanning signal lines (12A), a data signal line drive circuit (20A) for driving the data signal lines (11A), and a scanning signal line drive circuit (30A) for driving the scanning signal lines (12A) are provided for the display panel (10A). Data signal lines (11B), scanning signal lines (12B), a data signal line drive circuit (20B) for driving the data signal lines (11B), and a scanning signal line drive circuit (30B) for driving the scanning signal lines (12B) are provided for the display panel (10B). Input signal lines (17A and 17B) are provided so as not intersect each other in a plan view. This allows a reduction in power consumption and an increase in flexibility in design in a display panel which includes a plurality of display panels on a single substrate.

Abstract: A plurality of the display panels (10A and 10B) are provided on a single substrate. For each of the plurality of the display panels (10A and 10B), there are provided data signal lines (11A and 11B), scanning signal lines (12A and 12B), data signal line drive circuits (20A and 20B) which drive the respective data signal lines (11A and 11B) and scanning signal line drive circuits (30A and 30B) which drive the respective scanning signal lines (12A and 12B). This allows achievement of lower electric power consumption and greater design freedom in a display device including a plurality of display panels which are provided on a single substrate.