Patents by Inventor Shuji Nishi

Shuji Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090174372
    Abstract: In one embodiment of the present invention, a voltage source is disclosed including a lower output impedance is connected to a capacitive load via a switch element and a voltage source including a higher output impedance is connected to the capacitive load via a switch element. Until a potential of an output terminal attains a reference potential, a comparator keeps the switch element in an ON state so that the voltage source writes a potential onto the capacitive load. When the potential of the output terminal exceeds the reference potential, the comparator causes the switch element to be in an ON state so that the voltage source writes a potential onto the capacitive load so as to have a predetermined potential.
    Type: Application
    Filed: February 13, 2007
    Publication date: July 9, 2009
    Inventors: Kazuhiro Maeda, Ichiro Shiraki, Shinsaku Shimizu, Shuji Nishi
  • Publication number: 20090051678
    Abstract: A readily-mountable low-cost active matrix display apparatus with a setup function is provided. A serial interface circuit 20 and setup circuits 16 are each formed of TFT elements on a liquid crystal panel 11. The serial interface circuit 20 performs serial-parallel conversion on a setup control signal 17 serially inputted via setup terminals 15. The setup circuits 16 change the states of signals flowing in the liquid crystal panel 11 in accordance with signals outputted in parallel from the serial interface circuit 20. Thus, it is possible to change the potential, timing, etc., of signals inputted to or outputted from any peripheral circuits formed on the liquid crystal panel 11 or any peripheral circuits included in a semiconductor chip mounted on the surface of the liquid crystal panel 11.
    Type: Application
    Filed: April 3, 2006
    Publication date: February 26, 2009
    Inventors: Masakazu Satoh, Tomoyuki Nagai, Kazuhiro Maeda, Tamotsu Sakai, Shuji Nishi
  • Patent number: 6003054
    Abstract: A composite digital network including an integrating circuit, a summing circuit and a coefficient circuit is formed as an integrated circuit that provides a selected one of digital arithmetic circuits that perform different arithmetic operations depending upon coefficients of the coefficient circuits. A plurality of units of such composite digital networks may be connected in rows, columns or layers to provide an expanded network. In a method of producing such a composite digital network, basic digital arithmetic circuits that respectively correspond to various types of basic analog arithmetic circuits are defined based on Kirchhoff's rules, for example, and these basic digital arithmetic circuits are coupled to each other via a coefficient circuit to thus provide a generic digital arithmetic integrated circuit.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: December 14, 1999
    Assignee: Kanazawa Institute of Technology
    Inventors: Hiroyasu Oshima, Hodaka Murakoshi, Shuji Nishi