Patents by Inventor Shun-An Lin

Shun-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11919988
    Abstract: Provided is a thermoplastic polyether ester elastomer composition having a first chain represented by the following Formula (I) and a second chain represented by the following Formula (II), which are connected to each other: Wherein, the melting point of the thermoplastic polyether ester elastomer composition ranges from 80° C. to 160° C., and the enthalpy of fusion of the thermoplastic polyether ester elastomer composition is greater than 6 J/g. Production of the thermoplastic polyether ester elastomer composition has low energy consumption and facilitates smooth cutting strands into pellets, which is beneficial to mass production of the thermoplastic polyether ester elastomer composition.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 5, 2024
    Assignee: CHANG CHUN PLASTICS CO., LTD.
    Inventors: Chen-Yu Kuan, Chung-Hao Tseng, Te-Shun Lin
  • Publication number: 20240069387
    Abstract: A display device includes a touch panel, an optical adhesive layer, and a front light module that includes a light source and a light guide plate (LGP) including multiple microstructures recessed into the LGP from a first surface of the LGP to form voids. The optical adhesive layer is adhered between the touch panel and a first surface of the LGP. A surface of the optical adhesive layer facing the LGP is in contact with the first surface of the LGP in multiple first regions, and a surface of the optical adhesive layer facing the LGP and the plurality of microstructures being overlapped in multiple second regions. A maximum vertical distance between each void and the first surface is a first depth. A vertical distance between the first regions and the second regions is 0 to 0.7 times the first depth.
    Type: Application
    Filed: July 12, 2023
    Publication date: February 29, 2024
    Applicant: Coretronic Corporation
    Inventors: Tzeng-Ke Shiau, Yu-Feng Lin, Ying-Shun Syu, Che-Jui Hsu
  • Patent number: 11917923
    Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
  • Patent number: 11901899
    Abstract: A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2n?1 times.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: February 13, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Chi-Shun Lin
  • Patent number: 11822851
    Abstract: An information display system, an information display method, and a processing device are disclosed. The system includes a plurality of light-transmissive displays and a plurality of processing devices connected and communicating with each other through gateways. A first processing device is selected from the processing devices according to position information of a user, and determines sight line information of the user according to the position information and posture information of the user. A second processing device different from the first processing device calculates a target coordinate of a target. The first processing device selects a third processing device from the processing devices according to the sight line information of the user. The third processing device determines display position information of a virtual object according to a user coordinate and the object coordinate, and controls one of the displays to display the virtual object according to the display position information.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: November 21, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Hsuan Su, Yu-Hsiang Tsai, Hong-Ming Dai, Ya-Rou Hsu, Kai-Shun Lin
  • Patent number: 11823738
    Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: November 21, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Hsiu-Han Liao, Po-Yen Hsu, Chi-Shun Lin
  • Publication number: 20230306670
    Abstract: An embodiment of the present disclosure provides a game engine-based shading data processing method and apparatus, and an electronic device. The method includes: obtaining a rendering file obtained according to a pre-configured code editing template, where the pre-configured code editing template is fused at least with a first code editing rule and a second code editing rule, where the first code editing rule is used to edit pipeline data corresponding to a rendering manner, and the second code editing rule is used to edit a shader; based on the pipeline data and at least one first shader, generating a corresponding first intermediate file; and, when detecting a graphics drawing operation, performing graphics drawing processing according to the first intermediate file.
    Type: Application
    Filed: August 10, 2020
    Publication date: September 28, 2023
    Applicant: Xiamen Yaji Software Co., Ltd
    Inventors: Yunxiao Wu, Shun Lin
  • Patent number: 11764123
    Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Shang-Yun Hou, Tien-Yu Huang, Heh-Chang Huang, Kuan-Yu Huang, Shu-Chia Hsu, Yu-Shun Lin
  • Publication number: 20230289143
    Abstract: A memory device and a computing method are provided. The memory device includes a memory array, comprising a first and second memory blocks, and a comparator. The first memory block performs a multiplication and accumulation (MAC) operation according to a first weight matrix and a first input matrix to generate a first sum. The second memory block performs the MAC operation according to a second weight matrix and a second input matrix to generate a second sum. The comparator compares the first and second sums. In a first configuration, each value of the input and second input matrixes are the same and each value of the first and second weight matrixes are complements. In a second configuration, each value of the first and second input matrixes are complements and each value of the first and second weight matrixes are the same.
    Type: Application
    Filed: March 13, 2022
    Publication date: September 14, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Johnny Chan, Chi-Shun Lin
  • Publication number: 20230272173
    Abstract: Provided is a polyester composite film, comprising a first thermoplastic polyether ester elastomer (TPEE) film and a second TPEE film. The melting point of a second TPEE resin of the second TPEE film is higher than that of a first TPEE resin of the first TPEE film, and the absolute difference in enthalpy of fusion between the first and second TPEE films is 5 J/g to 15 J/g. By adopting the first and second TPEE films having specific absolute difference of the enthalpy of fusion and controlling the melting points of the first and second TPEE resins, the polyester composite film can be well attached onto the fabric by hot pressing to obtain sufficient peel strength, and thereby the attached fabric can have excellent waterproof performance. Besides, a hot melt adhesive laminate comprising the polyester composite film also exhibits the above beneficial effects when attached to the fabric.
    Type: Application
    Filed: August 18, 2022
    Publication date: August 31, 2023
    Inventors: Chung-Hao TSENG, Te-Shun LIN
  • Patent number: 11738268
    Abstract: A game development method and apparatus, a game running method and apparatus, and an electronic device. The game development method comprises: receiving a development instruction for a target function of a game (S101); obtaining a target prefabricated part corresponding to the target function from a preset database on the basis of the development instruction, a plurality of prefabricated parts being pre-stored in the database, each prefabricated part corresponding to one function setting, and each prefabricated part comprising a control configured with a preset logic, an application interface, and a backend invocation cloud function (S102); and developing the target function of the game according to the target prefabricated part (S103). According to the method, the development workload can be effectively reduced, the development labor cost and the later server maintenance cost are reduced, and thus the development efficiency is effectively improved.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 29, 2023
    Inventors: Zhe Wang, Shun Lin
  • Publication number: 20230214272
    Abstract: The present disclosure provides a game engine resource processing method and apparatus, an electronic device and a computer readable storage medium. The game engine resource processing method includes: by a first preset interface of a game engine, receiving an obtaining request for any game resource of any operation platform (S110); based on the obtaining request, obtaining any game resource by using a resource management system of the game engine, where the resource management system includes the first preset interface, resources, a resource manager, a resource loader and a resource registry (S120); returning any obtained game resource (S130).
    Type: Application
    Filed: August 7, 2020
    Publication date: July 6, 2023
    Applicant: Xiamen Yaji Software Co., Ltd
    Inventors: Hao Wang, Huabin Ling, Shun Lin
  • Patent number: 11694939
    Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Shang-Yun Hou, Tien-Yu Huang, Heh-Chang Huang, Kuan-Yu Huang, Shu-Chia Hsu, Yu-Shun Lin
  • Publication number: 20230207319
    Abstract: A method of fabricating a metal mask includes receiving a conductive substrate with a first surface, a second surface opposite to the first surface, a third surface connecting the first and second surfaces, and a fourth surface opposite to the third surface and connecting the first and second surfaces. The method further includes forming trenches in a direction from the first surface to the second surface and protrusions in the conductive substrate. The trenches and the protrusions are alternately arranged. The method further includes filling the trenches with an insulation material covering a first area of the protrusions, forming a metal layer on the conductive substrate overlying a second area different from the first area of the protrusions, removing the insulation material, and removing the conductive substrate. The metal layer becomes a metal mask with a three-dimensional structure including strip-shaped structures.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Inventors: Yun-Pei YANG, Jen-Shun LIN, Yu-Wei CHANG
  • Publication number: 20230183420
    Abstract: Provided is an aliphatic polyester composition. The aliphatic polyester composition comprises a polybutylene succinate, wherein the proton nuclear magnetic resonance of the aliphatic polyester composition has a first characteristic peak and a second characteristic peak. The first characteristic peak is located between 3.84 ppm and 4.32 ppm, and the second characteristic peak is located between 5.65 ppm and 5.85 ppm. The integral value of the first characteristic peak is set to be 100 and the integral value of the second characteristic peak is less than 0.10. By controlling the integral value of the second characteristic peak in H1-NMR of the aliphatic polyester composition, the aliphatic polyester composition has good appearance and low concentration of carboxylic acid end group and thereby the product value thereof is increased.
    Type: Application
    Filed: January 18, 2022
    Publication date: June 15, 2023
    Inventors: Jie-Cheng LI, Te-Shun LIN
  • Publication number: 20230178149
    Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 8, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Frederick Chen, Hsiu-Han Liao, Po-Yen Hsu, Chi-Shun Lin
  • Patent number: 11657864
    Abstract: An in-memory computing apparatus and a computing method thereof are provided. A memory array includes a shifted weight storage area that stores shifted weight values, a shift information storage area that stores the number of shift units, and a shift unit amount storage area that stores a shift unit amount. A shift restoration circuit restores a weight shift amount of a shifted sum-of-products according to the number of shift units of the shifted weight values and a column shift unit amount, so as to generate multiple restored sum-of-products.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 23, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Ming-Huei Shieh
  • Patent number: 11600346
    Abstract: A write cycle recording device includes a storage device and a controller. The storage device is corresponding to a memory block of a non-volatile memory. The storage device has a plurality of bits for recording a plurality of recorded writing loop counts corresponding to a plurality of writing operations of the memory block. The controller is configured to: perform a writing operation on the memory block; record a performed writing loop count of the writing operation; and, update a recorded writing loop count corresponding to the writing operation in the storage device according to the performed writing loop count.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 7, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Johnny Chan, Chi-Shun Lin
  • Publication number: 20230067548
    Abstract: A method of fabricating a metal mask includes receiving a metal planar substrate and patterning the metal planar substrate. The metal planar substrate includes a first surface and a second surface opposite to the first surface. The patterning the metal planar substrate includes forming strip-shaped structures, forming through holes, and forming a blind hole in a direction from the first surface to the second surface. The through holes extend to the first surface and the second surface. The through holes and the strip-shaped structures are alternately arranged. The blind hole extends across the through holes.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 2, 2023
    Inventors: Yun-Pei YANG, Jen-Shun LIN, Yu-Wei CHANG
  • Publication number: 20230067301
    Abstract: A mask manufacturing method includes the steps of: providing a substrate, wherein the substrate has a surface; forming a photoresist pattern on the substrate and covering a first part of the surface of the substrate with the photoresist pattern; providing a metal frame, wherein the metal frame has an inner wall enclosing a within-frame zone, and an area of the within-frame zone is smaller than an area of the surface of the substrate; assembling the metal frame and the substrate, so as to connect the inner wall with the surface and expose the photoresist pattern to the within-frame zone; and performing metal deposition in the within-frame zone and forming a deposited metal layer on the surface. The invention further provides a mask manufactured by the aforementioned mask manufacturing method.
    Type: Application
    Filed: December 29, 2021
    Publication date: March 2, 2023
    Inventor: JEN SHUN LIN