Abstract: The present invention discloses Fuke Qianjin Capsules and a quality control method therefor. The capsules are made of Radix Et Caulis Flemingiae, Caulis Mahoniae, Herba Andrographis, Zanthoxylum dissitum Hemsl., Caulis Spatholobi, Radix Angelicae Sinensis, Radix Codonopsis, and Radix Rosa Laevigata as raw materials. Each of the Fuke Qianjin Capsules contains not less than 2.0 mg of Z-ligustilide, and a total amount of andrographolide and dehydroandrographolide is not less than 1.9 mg. A new standard for controlling quality of the Fuke Qianjin Capsules has been established through an analysis of chemical ingredients in the Fuke Qianjin Capsules. This standard adds a variety of core ingredient content to the existing pharmacopoeia standards. According to the Fuke Qianjin Capsules made in this range, the consistency of effects between different batches is more stable. Moreover, the more the types of core ingredients are limited, the more stable the consistency of the drug effect.

Abstract: A method of forming a memory device includes forming a first electrode; forming a resistive switching layer over the first electrode; forming a dielectric layer over the resistive switching layer; forming a first opening in the dielectric layer, wherein the first opening passes through the dielectric layer and exposes the resistive switching layer; forming a first trench in the dielectric layer, wherein the first trench is directly above the first opening; and forming a second electrode having a step shape in the first opening and the first trench.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: Molecular-beam epitaxy (MBE) and more particularly suboxide MBE (S-MBE) and related structures are disclosed. S-MBE is disclosed that includes the use of a molecular beam of a suboxide that may be subsequently oxidized in a single step reaction to form an oxide film. By way of example, for a gallium oxide (Ga2O3) film, a molecular beam including a suboxide of gallium (Ga2O) may be provided. S-MBE may be performed in adsorption-controlled regimes where there is an excess of source material containing species in order to promote high growth rates for oxide films with improved crystallinity. Source mixtures for providing molecular beams of suboxides are disclosed that include mixtures of a particular element and an oxide of the element in ratios that promote such adsorption-controlled growth regimes. Related structures include oxide films having increased thickness with reduced crystal defects, including single polymorph films of gallium oxide.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h?1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail.

Abstract: In accordance with an embodiment, described herein is a system and method for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a management console component. The management console component can include a web application running in a script runtime environment, a plurality of backend of APIs for communicating with various nodes of the blockchain cloud service, and a plurality of client APIs configured to be invoked by a client application. The plurality of client APIs uses one or more of the plurality of backend APIs in provisioning the distributed ledger as a blockchain cloud service, and in managing the managing the blockchain cloud service.

Abstract: A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Abstract: A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h?1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: An authorization management method and apparatus, and an electronic device are provided. The method is applicable to a mobile terminal. A display screen of the mobile terminal is a bendable display screen and the display screen simultaneously displays an active authorization application and a passive authorization application. The method includes: monitoring whether the display screen is bent; and in a case that it is monitored that the display screen is bent, sending a first authorization confirmation instruction to the active authorization application such that the active authorization application provides an authorized account for the passive authorization application, and the passive authorization application acquires the authorized account from the active authorization application and performs a login through the account.

Abstract: An application processing method is performed at a computing device, the method including: displaying a first page of a first child application managed by a parent application, the first page of the first child application including a child application jump portal; detecting a child application jump operation corresponding to the first page in response to a user selection of the child application jump portal; presenting, in the first page candidate child application identifiers according to the child application jump operation; determining a child application identifier that is selected from the presented child application identifiers through a user selection operation; and generating, by using a second child application corresponding to the user-selected child application identifier, a second page that is displayed by covering the first page already displayed and that belongs to the second child application.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Abstract: A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.