Patents by Inventor Shuntaro Machida

Shuntaro Machida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6599830
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: July 29, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Patent number: 6479380
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Publication number: 20020164865
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Application
    Filed: July 3, 2002
    Publication date: November 7, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Publication number: 20020105085
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Application
    Filed: January 18, 2002
    Publication date: August 8, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
  • Patent number: 6358838
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: March 19, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama
  • Publication number: 20010046783
    Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
    Type: Application
    Filed: May 24, 2001
    Publication date: November 29, 2001
    Inventors: Takeshi Furusawa, Takao Kumihashi, Shuntaro Machida
  • Publication number: 20010009295
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 26, 2001
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama