Patents by Inventor Shuntaro Machida

Shuntaro Machida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080259733
    Abstract: A technology capable of improving receiver sensitivity and improving insulation withstand voltage in an ultrasonic transducer is provided. An ultrasonic transducer comprises: a lower electrode; an insulator covering the lower electrode; a cavity portion disposed on the insulator so as to overlap with the lower electrode; and an upper electrode disposed so as to overlap with the cavity portion. In this ultrasonic transducer, an insulator is inserted between the upper and lower electrodes in a part not having the cavity portion. By this means, sum total of thickness of insulators between the upper and lower electrodes in a part not having the cavity portion is larger than sum total of thickness of insulators between the upper and lower electrodes in a part having the cavity portion.
    Type: Application
    Filed: October 4, 2007
    Publication date: October 23, 2008
    Inventors: Shuntaro Machida, Hiroyuki Enomoto
  • Patent number: 7419902
    Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: September 2, 2008
    Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd
    Inventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
  • Patent number: 7411260
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 12, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Publication number: 20080079099
    Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.
    Type: Application
    Filed: July 6, 2007
    Publication date: April 3, 2008
    Inventors: Hiroyuki Enomoto, Taro Asai, Shuntaro Machida
  • Publication number: 20080042225
    Abstract: This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.
    Type: Application
    Filed: February 5, 2007
    Publication date: February 21, 2008
    Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki
  • Publication number: 20080001239
    Abstract: The performance of a sensor in a semiconductor device can be improved. A plurality of oscillators forming an ultrasonic sensor are arranged on a main surface of a semiconductor chip. A negative-type photosensitive insulating film which protects the oscillators is deposited on an uppermost layer of the semiconductor chip. At the time of exposure for forming an opening in the photosensitive insulating film, the semiconductor chip is divided into a plurality of exposure areas and exposed, and then, the exposure areas are jointed so that the entire area is exposed. At this time, a stitching exposure area is arranged so that a center of the stitching exposure area in a width direction in the joint portion of the adjacent exposure areas is positioned at a center of a line which connects centers of oscillators located above and below the stitching exposure area.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 3, 2008
    Inventors: Hiroyuki Enomoto, Katsuya Hayano, Shuntaro Machida
  • Publication number: 20070262401
    Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.
    Type: Application
    Filed: July 23, 2007
    Publication date: November 15, 2007
    Inventors: Natsuki Yokoyama, Shuntaro Machida, Yasushi Goto
  • Publication number: 20070222338
    Abstract: In an ultrasonic transducer including a gap between an upper electrode and a lower electrode on a silicon substrate, it is made possible to reduce or adjust warpage of an above-gap membrane vibrated by electrostatic actuation due to internal stress. A fourth insulating film and a fifth insulating film of films positioned above the gap which is a cavity required for transmitting and receiving ultrasonic are respectively a silicon oxide film for compression stress and a silicon nitride film for tensile stress. Therefore, compression stress and tensile stress cancel each other, so that warpage of the above-gap membrane is reduced. An amount of warpage can be adjusted by adjusting a film thickness of the fourth insulating film and a film thickness of the fifth insulating film.
    Type: Application
    Filed: January 23, 2007
    Publication date: September 27, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Takanori Aono, Tatsuya Nagata, Hiroyuki Enomoto, Shuntaro Machida
  • Patent number: 7270012
    Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: September 18, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Shuntaro Machida, Yasushi Goto
  • Publication number: 20070102831
    Abstract: The present invention has a object to enhance the yield and facilitate bonding in a device provided with micro-mechanical elements formed by a MEMS technique. According to the inveniton, when a first wafer having a plurality of areas in which micro-mechanical elements and pads are formed and a second wafer in which an aperture is formed are to be glued together, the aperture is shared by the pads in the plurality of areas. This makes it possible for individual chips, into which the wafer is cut out, to be bonded with a conventionally used wire bonder because a sufficient aperture is provided above the pads. Further according to the invention, at the step of dicing two glued wafers into individual chips, the two wafers are separately cut. This enables chipping of the wafers to be reduced and the yield at the dicing step to be enhanced.
    Type: Application
    Filed: December 24, 2003
    Publication date: May 10, 2007
    Inventors: Shuntaro Machida, Natsuki Yokoyama, Yasushi Goto
  • Publication number: 20070057600
    Abstract: A technique capable of obtaining an ultrasonic transducer at high sensitivity in which a plurality of ultrasonic oscillators M1 each comprising a lower electrode fixed above a substrate, a diaphragm opposed to the substrate with a cavity being put therebetween, and an upper electrode disposed to the diaphragm are arranged above one identical substrate to constitute an ultrasonic transducer and a concentric convex corrugated region having a center identical with the center for the diaphragm is disposed to the diaphragm in an outer side of the cavity exceeding 70% for the radius thereof.
    Type: Application
    Filed: August 4, 2006
    Publication date: March 15, 2007
    Inventors: Hiroshi Fukuda, Shuntaro Machida
  • Publication number: 20070057603
    Abstract: In a semiconductor diaphragm type electro-acoustic transducer device having no necessity for a DC bias voltage applied as a result of a charge-stored layer being provide between electrodes, electro-mechanical conversion efficiency undergoes a change owing to time-dependent change in a quantity of stored electricity due to leakage of charge, and so forth. As for sensitivity of signal reception, provided by an ultrasonic array-transducer made up of the electro-acoustic transducer devices each as a basic unit, not only a main beam sensitivity undergoes drift as a result of drift in the electromechanical conversion efficiency, but also there result deterioration in an acoustic S/N ratio, and deterioration in directionality of an ultrasonic beam.
    Type: Application
    Filed: July 24, 2006
    Publication date: March 15, 2007
    Inventors: Takashi Azuma, Shin-ichiro Umemura, Tatsuya Nagata, Hiroshi Fukuda, Shuntaro Machida, Toshiyuki Mine
  • Publication number: 20070052093
    Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.
    Type: Application
    Filed: July 20, 2006
    Publication date: March 8, 2007
    Inventors: Shuntaro Machida, Hiroyuki Enomoto, Yoshitaka Tadaki, Tatsuya Nagata
  • Publication number: 20060179640
    Abstract: A technology capable of preventing the degradation of operation reliability of CMUT when a lower electrode for CMUTs arranged in an array is divided in order to control the CMUTs independently is provided. Also, a technology capable of preventing the formation of a convex or concave distortion in an insulating film (membrane) of the cavity is provided. For its achievement, a size of a lower electrode divided for independently controlling each CMUT is set to be larger than that of a cavity. Also, a size of an upper electrode of the CMUT is set to be larger than that of the cavity.
    Type: Application
    Filed: December 27, 2005
    Publication date: August 17, 2006
    Inventors: Shuntaro Machida, Hiroshi Fukuda
  • Patent number: 7045843
    Abstract: Disclosed herein is a latchable MEMS switch device capable of retaining its ON or OFF state even after the external power source is turned off. It is unnecessary not only to introduce novel materials such as magnetic material but also to form complicated structures. At least one of the cantilever and pull-down electrode of a cold switch is connected to a second MEMS switch. A capacitor between the cantilever and pull-down electrode of the cold switch is charged by the second MEMS switch. Thereafter since the cold switch is isolated in the device, the charge remains stored. Therefore, the cold switch can remain in the ON state since the charge continues to create electrostatic attraction between the cantilever and the pull-down electrode.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: May 16, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Goto, Shuntaro Machida, Natsuki Yokoyama
  • Publication number: 20060070449
    Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.
    Type: Application
    Filed: September 29, 2005
    Publication date: April 6, 2006
    Inventors: Natsuki Yokoyama, Shuntaro Machida, Yasushi Goto
  • Publication number: 20050186801
    Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
    Type: Application
    Filed: April 13, 2005
    Publication date: August 25, 2005
    Inventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
  • Publication number: 20050067621
    Abstract: Disclosed herein is a latchable MEMS switch device capable of retaining its ON or OFF state even after the external power source is turned off. It is unnecessary not only to introduce novel materials such as magnetic material but also to form complicated structures. At least one of the cantilever and pull-down electrode of a cold switch is connected to a second MEMS switch. A capacitor between the cantilever and pull-down electrode of the cold switch is charged by the second MEMS switch. Thereafter since the cold switch is isolated in the device, the charge remains stored. Therefore, the cold switch can remain in the ON state since the charge continues to create electrostatic attraction between the cantilever and the pull-down electrode.
    Type: Application
    Filed: March 1, 2004
    Publication date: March 31, 2005
    Inventors: Yasushi Goto, Shuntaro Machida, Natsuki Yokoyama
  • Publication number: 20040048203
    Abstract: A method of manufacturing a semiconductor device is provided. In one example, the method includes fabricating holes and/or trenches in organosiloxane insulating film without damaging the film by ashing and without causing a problem of shape deterioration or obstacles. The method comprising forming a second insulating film and a inorganic thin film soluble to a dissolving solution on an organosiloxane insulating film, fabricating the organosiloxane insulating film using the inorganic thin film as a hard mask, and removing the hard mask after fabrication by a dissolving solution.
    Type: Application
    Filed: May 29, 2003
    Publication date: March 11, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Furusawa, Shuntaro Machida, Daisuke Ryuzaki
  • Patent number: 6680541
    Abstract: An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 20, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takeshi Furusawa, Daisuke Ryuzaki, Noriyuki Sakuma, Shuntaro Machida, Kenji Hinode, Ryou Yoneyama