Abstract: A processor includes a plurality of first processing units. The processor further includes a direct memory access unit coupled to a first processing unit of the plurality of first processing units. The processor further includes a data storage unit. The processor further includes a second processing unit adapted to process data transferred from the data storage unit, wherein the direct memory access unit is configured to transfer data stored in a memory to the data storage unit, the second processing unit is separate from the plurality of first processing units and the direct memory access unit, and the first processing unit of the plurality of first processing units and the second processing unit are configured to work in parallel. The processor further includes a first register configured to store data corresponding to an interrupt request related to the second processing unit or the data storage unit.

Abstract: The present invention provides an anti-shock pad, which includes: a board-shaped compound material structure, manufactured by mixing a composition and foam molding the composition, wherein the composition comprises: a main substrate, having a proportion of 50 wt % to 80 wt % of total weight of the composition, comprising: a vinyl acetate; and an ethylene-vinyl acetate; a secondary substrate, having a proportion of 10 wt % to 40 wt % of the total weight of the composition, comprising: a polyethylene; a styrene butadiene rubber; and a thermoplastic elastomer; and an additive, having a proportion of 1 wt % to 20 wt % of the total weight of the composition; wherein a density of the anti-shock pad is between 0.20 and 0.50, and a foaming ratio of the anti-shock pad is between 20 and 40. The present invention is also related to a method of manufacturing the anti-shock pad.

Abstract: A processor includes a plurality of first processing units. The processor further includes a direct memory access unit coupled to a first processing unit of the plurality of first processing units. The processor further includes a data storage unit. The processor further includes a second processing unit adapted to process data transferred from the data storage unit, wherein the direct memory access unit is configured to transfer data stored in a memory to the data storage unit, the second processing unit is separate from the plurality of first processing units and the direct memory access unit, and the first processing unit of the plurality of first processing units and the second processing unit are configured to work in parallel. The processor further includes a first register configured to store data corresponding to an interrupt request related to the second processing unit or the data storage unit.

Abstract: A processor includes a plurality of first processing units. A direct memory access unit is coupled to at least one first processing unit of the plurality of first processing units. The processor includes a plurality of data storage units. A second processing unit is adapted to process data from at least one data storage unit of the plurality of data storage units. The direct memory access unit is configured to transfer data stored in a memory to the at least one data storage unit of the plurality of data storage units. The second processing unit is separate from the plurality of first processing units and the direct memory access unit. The at least one first processing unit and the second processing unit are configured to work in parallel. The processor further includes a first register. The second processing unit is configured to receive an operation signal from the first register.

Abstract: A constituent for producing a shock-absorbing composite material comprises 50-80 wt % primary matrix including vinyl acetate; ethylene/vinyl acetate copolymer; 10-40 wt % secondary matrix including polyethylene; styrene-butadiene rubber; a thermoplastic elastomer; and 1-20 wt % additive. A shock-absorbing composite material which contains the constituent and a production method thereof are further introduced. The shock-absorbing composite material is applicable to sports equipment (say, shoe pads, clubs and rackets), medical care (say, care-oriented clothes for the elderly, the sick, the injured, and the handicapped), and applications related to impact protection (say, helmets and bumpers.) The shock-absorbing composite material is applied to defense industry.

Abstract: The present invention provides an anti-shock pad, which includes: a board-shaped compound material structure, manufactured by mixing a composition and foam molding the composition, wherein the composition comprises: a main substrate, having a proportion of 50 wt % to 80 wt % of total weight of the composition, comprising: a vinyl acetate; and an ethylene-vinyl acetate; a secondary substrate, having a proportion of 10 wt % to 40 wt % of the total weight of the composition, comprising: a polyethylene; a styrene butadiene rubber; and a thermoplastic elastomer; and an additive, having a proportion of 1 wt % to 20 wt % of the total weight of the composition; wherein a density of the anti-shock pad is between 0.20 and 0.50, and a foaming ratio of the anti-shock pad is between 20 and 40. The present invention is also related to a method of manufacturing the anti-shock pad.

Abstract: A constituent for producing a shock-absorbing composite material comprises 50-80 wt % primary matrix including vinyl acetate; ethylene/vinyl acetate copolymer; 10-40 wt % secondary matrix including polyethylene; styrene-butadiene rubber; a thermoplastic elastomer; and 1-20 wt % additive. A shock-absorbing composite material which contains the constituent and a production method thereof are further introduced. The shock-absorbing composite material is applicable to sports equipment (say, shoe pads, clubs and rackets), medical care (say, care-oriented clothes for the elderly, the sick, the injured, and the handicapped), and applications related to impact protection (say, helmets and bumpers.) The shock-absorbing composite material is applied to defense industry.

Abstract: An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier.

Abstract: A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.

Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.

Abstract: A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.

Abstract: A processor includes a plurality of first processing units. A direct memory access unit is coupled to at least one first processing unit of the plurality of first processing units. The processor includes a plurality of data storage units. A second processing unit is adapted to process data from at least one data storage unit of the plurality of data storage units. The direct memory access unit is configured to transfer data stored in a memory to the at least one data storage unit of the plurality of data storage units. The second processing unit is separate from the plurality of first processing units and the direct memory access unit. The at least one first processing unit and the second processing unit are configured to work in parallel. The processor further includes a first register. The second processing unit is configured to receive an operation signal from the first register.

Abstract: An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers.

Abstract: An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier.

Abstract: Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.

Abstract: An integrated circuit system comprises an interposer, a first integrated circuit, and at least one voltage regulator module. The first integrated circuit comprises first bond pads, and is electrically connected to the interposer at a first position of the interposer via the first bond pads. The first integrated circuit also comprises second bond pads. The first integrated circuit further comprises at least two circuit blocks. The at least two circuit blocks are configured to operate at different operating voltages. The at least one voltage regulator module is electrically connected to the first integrated circuit via the second bond pads, and the at least one voltage regulator module is configured to convert a received power supply voltage to the respective operating voltage of one of the at least two circuit blocks and supply the respective operating voltage via the second bond pads.

Abstract: An integrated circuit includes a circuit and a guard ring. The circuit is over a substrate. The guard ring surrounds the circuit and includes a staggered line. The staggered line comprises a first zigzag line and a second zigzag line. The first zigzag line comprises interconnections formed in at least two GDS layers. The second zigzag line comprises interconnections formed in at least two GDS layers. The first zigzag line and the second zigzag line form a first quadrangle and a second quadrangle.

Abstract: An information processor includes a plurality of first processing units; and a direct memory access unit coupled to at least one first processing unit. The information processor includes at least one first memory unit coupled to the direct memory access unit. The first memory unit includes a second memory unit. The first memory unit includes a second processing unit for processing data stored in the second memory unit. The second memory unit is adapted to be accessed by at least one first processing unit through the direct memory access unit, and the second processing unit is separate from the plurality of first processing units and the direct memory access unit. The first memory unit includes at least one register to be accessed by the at least one first processing unit and the second processing unit. The second processing unit is for receiving operation instructions from the at least one register.

Abstract: An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers.