Patents by Inventor Shyh An Chi
Shyh An Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140375408Abstract: An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers.Type: ApplicationFiled: June 20, 2013Publication date: December 25, 2014Inventors: Hsiao-Tsung YEN, Shyh-An CHI
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Publication number: 20140333355Abstract: A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.Type: ApplicationFiled: July 28, 2014Publication date: November 13, 2014Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Patent number: 8836390Abstract: An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.Type: GrantFiled: September 27, 2013Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Patent number: 8816731Abstract: An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.Type: GrantFiled: September 12, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Patent number: 8803581Abstract: A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.Type: GrantFiled: April 12, 2010Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shyh-An Chi, Shiue Tsong Shen, Jeff Lee, Frank Y. Lee
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Publication number: 20140210077Abstract: An integrated circuit system comprises an interposer, a first integrated circuit, and at least one voltage regulator module. The first integrated circuit comprises first bond pads, and is electrically connected to the interposer at a first position of the interposer via the first bond pads. The first integrated circuit also comprises second bond pads. The first integrated circuit further comprises at least two circuit blocks. The at least two circuit blocks are configured to operate at different operating voltages. The at least one voltage regulator module is electrically connected to the first integrated circuit via the second bond pads, and the at least one voltage regulator module is configured to convert a received power supply voltage to the respective operating voltage of one of the at least two circuit blocks and supply the respective operating voltage via the second bond pads.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shyh-An CHI, Mark Shane PENG, Yun-Han LEE
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Publication number: 20140207992Abstract: An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core. The at least one tightly coupled smart memory unit includes a memory unit, and a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Shyh-An CHI
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Publication number: 20140145757Abstract: An integrated circuit die stack comprises a first die and a second die connected to each other. Each of the first and second dies comprise a functional circuitry, a plurality of first contacts on a first surface of the respective die, a plurality of second contacts on a second surface of the respective die, and a programmable array coupled to the functional circuitry and the plurality of first and second contacts. The programmable array includes a plurality of programmable connection elements in the first and second dies. The programmable connection elements are programmed to bypass one of the first and second dies.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Shyh-An CHI
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Patent number: 8719463Abstract: An information processor includes a central processing unit core and a tightly coupled smart memory unit, the central processing unit core having a direct memory access unit. The tightly coupled smart memory unit having a memory unit coupled to the central processing unit core and a control register, and status register coupled to the central processing unit core and a local processing unit that processes data stored in the memory unit.Type: GrantFiled: November 16, 2010Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Shyh-An Chi
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Patent number: 8716855Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.Type: GrantFiled: November 10, 2010Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shyh-An Chi, Mark Shane Peng, Yun-Han Lee
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Publication number: 20140091834Abstract: An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.Type: ApplicationFiled: December 10, 2013Publication date: April 3, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shyh-An CHI
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Patent number: 8669780Abstract: The embodiments described provide connection structures for dies in an integrated circuit die stack. Each die in the die stack includes a functional circuitry, a programmable array and a programmable array control unit. By triggering the programmable array control unit to program corresponding programmable array in each die of the die stack, signal routes are orchestrated to connect to corresponding functional circuitry in each die of the die stack to enable the entire die stack to meet functional goals. In addition, specific die(s) in the die stack may be bypassed by issuing control command to the programmable array control unit. Die(s) may be bypassed to meet functional goals and to improve yield, and reliability.Type: GrantFiled: November 15, 2011Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Shyh-An Chi
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Publication number: 20140021989Abstract: An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.Type: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Publication number: 20140015576Abstract: An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Publication number: 20140015599Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee, Yun-Han Lee
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Patent number: 8624626Abstract: An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.Type: GrantFiled: November 14, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shyh-An Chi
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Patent number: 8552795Abstract: A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.Type: GrantFiled: June 4, 2010Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee, Yun-Han Lee
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Patent number: 8547151Abstract: A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.Type: GrantFiled: February 28, 2012Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Publication number: 20130135018Abstract: A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.Type: ApplicationFiled: February 28, 2012Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Publication number: 20130120021Abstract: An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shyh-An CHI