Abstract: An HDPCVD oxide layer is deposited over metal lines on a semiconductor substrate. The HDPCVD oxide layer so deposited has ridged portions over the metal lines. The HDPCVD oxide layer is then treated in-situ with an inert gas or reactive gas plasma to remove the ridged portions on the surface. A sacrificial dielectric layer can then be deposited on the HDPCVD oxide layer with good step coverage, thereby to eliminate voids.

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A method of forming a dual damascene opening, comprising the following steps. A semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract: A method for forming a metal capacitor in a damascene process is provided. Before the metal capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. The stacked layers are then subjected to a masking process and an etching process to form the thin-film capacitor and the metal wire with the remaining insulator and the remaining second metal layer thereon. The remaining second metal layer located on the metal wire is removed by another masking process and another etching process. After forming the capacitor and the metal wire, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: This invention provides a method for forming a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A deposition process for silicon oxycarbide films suitable for use as anti-reflection coatings is described. The, process is based on plasma enhanced CVD of silane mixed with methyl-silane, trimethyl-silane, or tetramethyl-silane (together with a carrier gas). Provided the relative gas flow rates are maintained within the ranges specified, films having excellent ARL properties are obtained, with photoresist patterns formed on said films being free of overhangs and footings.

Abstract: The present invention provides a method for fabricating a metal capacitor. A first level metal layer is formed on a substrate. Then, the first level metal layer is patterned to concurrently form a first metal line and a second metal line. The second metal line defines a metal capacitor region and is used as a lower electrode of the metal capacitor. Then, an insulating layer is conformably formed on the substrate, the first metal line, and the second metal line. A first intermetal dielectric layer is formed on the insulating layer. Then, the first intermetal dielectric layer is subjected to planarization treatment such that the planarization treatment finally exposes the insulating layer. Finally, a third metal line is formed on the insulating layer in the metal capacitor region such that the third metal line is used as the upper electrode of the metal capacitor.

Abstract: This invention provides a method for forming a metal capacitor with a damascene process. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by the following steps. An opening for a capacitor is formed in a second insulator. Then, a first metal layer, a dielectric layer and a second metal layer are conformally formed in the opening on the second insulator. The stacked layers are subjected to a chemical mechanical polishing process until the second insulator is exposed. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A process for removing all amino groups adsorbed on a surface is described. The key feature of the invention is exposure of a layer, particularly an anti-reflection coating that has been deposited by means of PECVD, to a high-density plasma of either argon, oxygen, or a mixture of both. When this is done according to the teachings of the invention, all amino groups are removed from the surface and further processing of photoresist can then be initiated. Even if delays are introduced during subsequent further photoresist processing, dimensionally stable patterns are obtained.

Abstract: This invention is a heterobifunctional artificial cornea or biomedical membrane and novel process for preparing the heterobifunctional artificial cornea. In this method, plasma induced graft polymerization is adopted to provide the surface property modification of polymer materials like silicone or polyurethane. At first, the frontal side of the material is grafted with polyacrylic acid or polymethacrylic acid and then bonded with collagen, or 2-hydroxyethylmethacrylate (HEMA) is grafted alone. A surface which increases the cell attachment and growth can be then developed. Another side of this membrane is grafted with acrylic acid or polymethacrylic acid and then different molecular weights of polyethylene oxide (PEO) is bonded thereto. 2-methacryloyl-oxyethyl phosphoryl chloride (2-MPC) is grafted to the membrane.