Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices with an electrode having tapered sides. The present disclosure provides a memory device including a first electrode having a tapered shape and including a tapered side, a top surface, and a bottom surface, in which the bottom surface has a larger surface area than the top surface, a resistive layer on and conforming to at least the tapered side of the first electrode, and a second electrode laterally adjacent to the tapered side of the first electrode, the second electrode including a top surface and a side surface abutting the resistive layer, in which the side surface forms an acute angle with the top surface.

Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.

Abstract: A nonvolatile memory device is provided. The device comprises a memory transistor. A first capacitor is coupled to the memory transistor. A second capacitor is coupled to the memory transistor. The second capacitor comprises a first electrode and a second electrode. The first capacitor and the second capacitor are connected to separate input terminals.

Abstract: The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a dual-gate transistor and a memory cell. The memory cell is adjacent to the dual-gate transistor, wherein the memory cell and the dual-gate transistor share a common electrode.

Abstract: A memory device may be provided, including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.

Abstract: A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.

Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged below a control gate, and between an erase gate and a word line. A first side portion of the floating gate and a second side portion of the floating gate may extend laterally beyond the control gate in substantially equal amounts. The erase gate may overhang the first side portion of the floating gate. A first control gate spacer may be arranged between the control gate and the word line. The first control gate spacer may at least partially cover a top surface of the second side portion of the floating gate.

Abstract: A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells.

Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

Abstract: The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode.

Abstract: Structures for a split gate flash memory cell and methods of forming a structure for a split gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source/drain regions are formed in the semiconductor substrate. A first gate is laterally positioned between the trench and the second source/drain region, and a second gate includes a portion inside the trench. The first source/drain region is located in the semiconductor substrate beneath the trench. A dielectric layer is positioned between the portion of the second gate inside the trench and the semiconductor substrate.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element includes a first switching layer, a second switching layer, a conductive spacer, a first electrode, and a second electrode. The first switching layer includes a portion positioned between the first electrode and the conductive spacer, the second switching layer includes a portion positioned between the second electrode and the conductive spacer, and the conductive spacer is positioned between the portion of the first switching layer and the portion of the second switching layer.

Abstract: Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.