Patents by Inventor Shyue Seng Tan

Shyue Seng Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile memory bit cells with non-rectangular floating gates
    Patent number: 11158643
    Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Kiok Boone Elgin Quek, Xinshu Cai, Eng Huat Toh
  • Memory device and a method for forming the memory device
    Patent number: 11152380
    Abstract: A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 19, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Bin Liu, Shyue Seng Tan
  • RRAM DEVICES AND METHODS OF FORMING RRAM DEVICES
    Publication number: 20210313512
    Abstract: A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: Xinshu CAI, Shyue Seng TAN, Eng Huat TOH
  • Semiconductor non-volatile memory devices
    Patent number: 11139311
    Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 5, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yongshun Sun, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Neuromorphic memories with split gate flash multi-level cell and method of making the same
    Patent number: 11119917
    Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 14, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Shyue Seng Tan, Xinshu Cai, Fan Zhang, Soh Yun Siah, Tze Ho Simon Chan
  • MEMORY DEVICES AND METHODS OF FORMING MEMORY DEVICES
    Publication number: 20210273160
    Abstract: A memory device may be provided including one or more bottom electrodes, one or more mask elements, one or more top electrodes and a switching layer. The bottom electrode(s) may include a first bottom electrode, the mask element(s) may include a first mask element and the top electrode(s) may include a first top electrode. The first mask element may be arranged over a first part of the first bottom electrode. The first top electrode may be arranged over and in contact with the first mask element. The switching layer may be arranged to extend over a second part of the first bottom electrode, and along a first side surface of the first mask element and further along a first side surface of the first top electrode. The first side surfaces of the first mask element and the first top electrode may face a same direction.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Desmond Jia Jun LOY, Eng Huat TOH, Shyue Seng TAN
  • SEMICONDUCTOR NON-VOLATILE MEMORY DEVICES
    Publication number: 20210257377
    Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: YONGSHUN SUN, ENG HUAT TOH, SHYUE SENG TAN, KIOK BOONE ELGIN QUEK
  • Methods of forming a thyristor-based random access memory using fin structures and elevated layers
    Patent number: 11094696
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek, Danny Pak-Chum Shum
  • SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES
    Publication number: 20210247470
    Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Inventors: Ping ZHENG, Eng Huat TOH, Kazutaka YAMANE, Shyue Seng TAN, Kiok Boone Elgin QUEK
  • Memory cells with extended erase gate, and process of fabrication
    Patent number: 11088156
    Abstract: A flash memory device is provided. The device comprises a substrate and a source region in the substrate. A first gate stack is positioned above the substrate and adjacent to the source region. A dual function gate structure having an upper portion and a lower portion is positioned above the source region. The upper portion of the dual function gate structure overlaps the first gate stack and the lower portion is adjacent to the first gate stack. A second gate is positioned above the substrate on an opposite side of the first gate stack from the dual function gate. A drain region is in the substrate adjacent to the second gate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Kiok Boone Elgin Quek, Eng Huat Toh
  • MEMORY DEVICES AND METHODS OF FORMING MEMORY DEVICES
    Publication number: 20210225936
    Abstract: A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: Lanxiang WANG, Shyue Seng TAN, Eng Huat TOH, Benfu LIN
  • Non-volatile memory elements with a multi-level cell configuration
    Patent number: 11069743
    Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. A first non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A second non-volatile memory element includes a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the second electrode of the first non-volatile memory element.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 20, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • SEMICONDUCTOR DEVICES WITH MEMORY CELLS
    Publication number: 20210217859
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure provides a semiconductor device including an isolation region disposed on a substrate, a pair of diffusion structures disposed upon the isolation region, a dielectric layer that covers side surfaces of the diffusion structures, and a gate structure disposed on the dielectric layer and between the diffusion structures, where the gate structure is electrically coupled to the diffusion structures.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 15, 2021
    Inventors: WEI CHANG, ENG HUAT TOH, SHYUE SENG TAN
  • DUAL BIT MEMORY DEVICE WITH TRIPLE GATE STRUCTURE
    Publication number: 20210217865
    Abstract: A memory device is provided. The device comprises a semiconductor fin with a first gate and a second gate disposed over the semiconductor fin. A third gate is positioned over the semiconductor fin and a lower portion of the third gate is disposed between the first and second gates.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 15, 2021
    Inventors: XINSHU CAI, SHYUE SENG TAN, ENG HUAT TOH
  • Sensors having resistive elements
    Patent number: 11063158
    Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 13, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Semiconductor devices with ion-sensitive field effect transistor
    Patent number: 11054387
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices integrated with an ion-sensitive field-effect transistor (ISFET) and methods of forming the same. The semiconductor device may include a substrate, a reference gate structure disposed above the substrate, a floating gate structure disposed above the substrate and adjacent to the reference gate structure, where the reference gate structure is electrically coupled to the floating gate structure, and a dielectric layer disposed between the reference gate structure and the floating gate structure.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Logic gate devices and methods of forming a logic gate device
    Patent number: 11050426
    Abstract: According to various embodiments, a logic gate device includes a transistor, a first resistor, a second resistor and a third resistor. The first resistor is connected between a first input terminal of the logic gate device and a gate terminal of the transistor. The second resistor is connected between a second input terminal of the logic gate device and the gate terminal. The third resistor is connected between a voltage supply terminal and a first terminal of the transistor. The logic gate device is configured to generate an output voltage at the first terminal based on input voltages received at the first input terminal and the second input terminal.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • SENSORS HAVING RESISTIVE ELEMENTS
    Publication number: 20210184059
    Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: LANXIANG WANG, ENG HUAT TOH, SHYUE SENG TAN, KIOK BOONE ELGIN QUEK
  • ON-CHIP TEMPERATURE SENSING WITH NON-VOLATILE MEMORY ELEMENTS
    Publication number: 20210164845
    Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Bin Liu, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • NON-VOLATILE MEMORY ELEMENTS WITH ONE-TIME OR MULTIPLE-TIME PROGRAMMABILITY
    Publication number: 20210167069
    Abstract: Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Sriram Balasubramanian, Shyue Seng Tan