Patents by Inventor Siamack Nemazie

Siamack Nemazie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150253999
    Abstract: In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Siamack Nemazie, Mehdi Asnaashari, Ruchirkumar D. Shah
  • Publication number: 20150248349
    Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD) and is addressable using physical addresses associated with user data that are provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of the user data in the physically-addressed SSD. The flash tables are maintained in the non-volatile memory modules.
    Type: Application
    Filed: April 27, 2015
    Publication date: September 3, 2015
    Inventor: Siamack Nemazie
  • Publication number: 20150248348
    Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD) and is addressable using physical addresses associated with user data that are provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of the user data in the physically-addressed SSD. The flash tables are maintained in the non-volatile memory modules.
    Type: Application
    Filed: April 27, 2015
    Publication date: September 3, 2015
    Inventor: Siamack Nemazie
  • Publication number: 20150248346
    Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD) and is addressable using physical addresses associated with user data that are provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of the user data in the physically-addressed SSD. The flash tables are maintained in the non-volatile memory modules.
    Type: Application
    Filed: April 27, 2015
    Publication date: September 3, 2015
    Inventor: Siamack Nemazie
  • Publication number: 20150220386
    Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao Yang
  • Publication number: 20150220435
    Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
  • Publication number: 20150212752
    Abstract: A storage system includes a storage processor coupled to solid state disks (SSDs) and a host, the SSDs are identified by SSD logical block addresses (SLBAs). The storage processor receives a command from the host to write data to the SSDs and further receives a location within the SSDs to write the data, the location being referred to as a host LBA. The storage processor includes a central processor unit (CPU) subsystem and maintains unassigned SLBAs of a corresponding SSD. The CPU subsystem upon receiving the command to write data, generates sub-commands based on a range of host LBAs derived from the received command and further based on a granularity. At least one of the host LBAs is non-sequential relative to the remaining host LBAs. The CPU subsystem assigns the sub-commands to unassigned SLBAs by assigning each sub-command to a distinct SSD of a stripe, the host LBAs being decoupled from the SLBAs.
    Type: Application
    Filed: April 3, 2015
    Publication date: July 30, 2015
    Inventors: Siamack Nemazie, Mehdi Asnaashari, Ruchirkumar D. Shah
  • Publication number: 20150212734
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
  • Patent number: 9083382
    Abstract: A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: July 14, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventor: Siamack Nemazie
  • Publication number: 20150169230
    Abstract: A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 18, 2015
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Ruchirkumar D. Shah
  • Publication number: 20150169244
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Patent number: 9058257
    Abstract: A method of configuring a computer memory system includes receiving a request from customized software driver or a BIOS extension software or a customized legacy BIOS or a customized UEFI PMM extension software or a customized UEFI BIOS, scanning memory module sockets in response to the request, recognizing memory modules in the memory module sockets, the memory modules being made of, at least in part, persistent memory modules (PMMs), configuring the PMMs to be invisible to the OS, and storing the mapping information to a designated protected persistent memory area, and presenting the PMMs as a persistent block storage to the OS.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 16, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Ngon Van Le
  • Publication number: 20150143038
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing stripping across the SSDs.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 21, 2015
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Patent number: 9037786
    Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 19, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
  • Patent number: 9037787
    Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 19, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventor: Siamack Nemazie
  • Patent number: 9015553
    Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: April 21, 2015
    Assignee: Round Rock Research, LLC
    Inventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao Yang
  • Patent number: 9015356
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 21, 2015
    Assignee: Micron Technology
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
  • Patent number: 9009397
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Patent number: 9009396
    Abstract: A computer system includes a central processing unit (CPU), a system memory coupled to the CPU and including flash tables, and a physically-addressable solid state disk (SSD) coupled to the CPU. The physically-addressable SSD includes a flash subsystem and a non-volatile memory and is addressable using physical addresses. The flash subsystem includes one or more copies of the flash tables and the non-volatile memory includes updates to the copy of the flash tables. The flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressable SSD, wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Publication number: 20150095555
    Abstract: A method of thin provisioning in a storage system is disclosed. The method includes communicating to a user a capacity of a virtual storage, the virtual storage capacity being substantially larger than that of a storage pool. Further, the method includes assigning portions of the storage pool to logical unit number (LUN) logical block address (LBA)-groups only when the LUN LBA-groups are being written to and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.
    Type: Application
    Filed: February 3, 2014
    Publication date: April 2, 2015
    Applicant: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Ruchirkumar D. Shah, Siamack Nemazie