Abstract: A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

Abstract: A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

Abstract: A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

Abstract: In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

Abstract: A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO2layer disposed on the optional silicon nitride film or on the silicon layer and the silicon germanium layer, when the optional silicon nitride film is not present.

Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided.

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Abstract: A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

Abstract: An improved trench capacitor and method of fabrication are disclosed. The trench capacitor utilizes a rare-earth oxide layer to reduce depletion effects, thereby improving performance of the trench capacitor.

Abstract: In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.