INSULATING LAYERS ON DIFFERENT SEMICONDUCTOR MATERIALS
A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO2layer disposed on the optional silicon nitride film or on the silicon layer and the silicon germanium layer, when the optional silicon nitride film is not present.
Latest IBM Patents:
This application is a divisional of U.S. Ser. No. 12/685,332, filed Jan. 11, 2010, the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention relates to methods of creating insulating layers for semiconductor device structures, and particularly for field effect transistor structures formed on a same substrate. The present invention relates also to semiconductor structures created during the methods.
BACKGROUND OF THE INVENTIONHigh performance logic device structures often include embedded SiGe channels in the pFETs while the nFETs are constructed on conventional single crystal substrates. To construct multiple gate oxides (so called double gate architectures) on embedded SiGe channels and on Si channels requires that the gate insulators/dielectrics be deposited, for example, by means of chemical vapor deposition (CVD). CVD techniques are used in order to construct devices with comparable physical thicknesses. If the double gate oxides are constructed by means of thermal oxidation (in a manner consistent with non-SiGe channel technologies), then the differing oxidation rates of the SiGe and Si will result in devices with different characteristics (Tiny, Vt, Ion/Ioff etc.). These different characteristics are often problematic.
In most cases, the CVD oxides deposited on SiGe channels are so called “high temperature oxides” or HTOs. HTOs can be deposited in either single wafer or batch furnace type tools. HTOs are typically produced through a reaction of SiH4 or Si2H6 with N2O, O2 or H2O at reduced pressures such as 200 Torr and temperatures between 600° C. and 800° C.
It is often reported that HTO layers are of lower quality when compared to SiO2 films (layers) produced by means of thermal oxidation of single crystal substrates. The lower film quality is manifested in higher trap densities (in the bulk of the film and the interface) which often leads to reduced reliability metrics, e.g. Vbd, TDDB, NBTI, etc. This reduced reliability, therefore, generally precludes the use of HTOs in high performance CMOS transistor applications.
SUMMARY OF THE INVENTIONThe present invention is directed to processes for (methods of) creating high quality SiO2 films and interfaces in high performance CMOS technologies which use SiGe (or some other semiconducting material such as SiC, GaAs, etc.) which results in differing oxidation rates on the n-FET region and p-FET region and, thereby, precludes the use of conventional thermal oxidation to create the FET devices.
The inventive processes described through embodiments herein are based on the deposition of a thin layer of a sacrificial material, e.g., Si3N4. The thin layer is deposited in a continuous film ranging from a single monolayer to any desired thickness. In the embodiments, the continuous film of the sacrificial material preferably is conformal with the underlying materials. The sacrificial material is then oxidized to a thickness which consumes (preferably, completely) the sacrificial film but does not oxidize more than ten (10) angstroms into the underlying SiGe material. Because the gate dielectric is created by means of the thermal oxidation of the sacrificial material, the composition of the finished (oxidized in this case) material is not dictated by the transport of, the ratio of, or the purity of process gasses, but rather by: 1) the availability of Si in the starting material, and 2) the presence of a suitable oxidant.
The inventors believe films and interfaces created according to embodiments of the present invention will be of a higher quality than CVD deposited oxides (e.g., HTOs) and may be employed in integration arrangements requiring multiple gate oxides disposed on channels constructed of dissimilar materials.
According to a preferred embodiment of the present invention, a method of creating insulating layers on different semiconductor materials includes: providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material; and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than ten (10) angstroms into the second material. More preferably, the sacrificial layer is converted entirely into SiO2 without oxidizing any of the second material.
It is a principal object of the present invention to provide a method of creating oxides having at least approximately (±10%) equal or equal thicknesses on different semiconductor materials.
It is a further object of the present invention to provide such a method that is highly compatible with conventional methods/processes for producing nFETs and pFETs on a same substrate.
Further and still other objects of the present invention will become more readily apparent when the following description is taken in conjunction with the drawing figures.
Turning now to
In the preferred embodiment, the chemical composition of the region 14, for example, includes or preferably consists essentially of Si, while the chemical composition of the region 13 includes or preferably consists essentially of SiGe.
In
The embodiment disclosed herein uses MLD Si3N4 but can be performed well with other sacrificial materials which can be deposited sufficiently thin and continuous, and which can be converted to SiO2 via known thermal or plasma techniques. Such sacrificial materials include, for example, amorphous silicon, polycrystalline silicon, or silicon carbide. Such other sacrificial materials can be deposited using tools such as tool model “SinGen” commercially available from Applied Materials, Inc. (AMAT). Also, the thermal or plasma techniques can be performed using tools such as tool model “Radiance” or “DPN” commercially available from Applied Materials, Inc. (AMAT). Those skilled in the art can readily effect the deposition, thermal and/or plasma techniques in view of the present specification and drawing figures.
In
DPN is Decoupled Plasma Nitridation.
PNA is Post Nitridation Anneal.
DPN and PNA steps are well known in the semiconductor manufacturing process art.
In
For discussions of various conventional/known techniques for creating a nFET and a pFET on a same substrate, see for example:
-
- U.S. Pat. No. 7,057,216B2 incorporated by reference in its entirety herein;
- U.S. Pat. No. 5,547,894 incorporated by reference in its entirety herein;
- Fundamentals of Semiconductor Processing Technologies, by Badih El-Korch (Kluwer Academic Publishers, 1997), and
- VLSI Technology, by S. M. SZE (McGraw Hill, 1988, ISBN 0-07-062 735-5).
Finally,
Example Tools and Parameters for the preferred embodiment of the present invention in a 32 nm Technology Mode include, for example:
MLD Si3N4 deposition is performed at 500 C. Silicon Nitride films are deposited by exposing wafers to alternating flows of dichlorosilane (DCS) and ammonia plus RF power. Typical conditions are 1 slm of DCS and 5 slm of NH3 with 100 W of RF power. The thickness of the layer 15 is determined by controlling, e.g., the number of cycles (i.e. number of thin films deposited).
Radical oxidation (Applied Materials, Inc. tool trade name “ISSG”) is performed at 900 C, at pressure of 7 T, and with a H2 concentration of 5% (500 sccm H2 in 9.5 slm 02). The thickness T of the layer 17 is determined by controlling temperature, H2 concentration and/or process time. All these controls would be well understood by those skilled in the art, in view of the present specification and drawing figures.
While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims. For example, the invention can be readily applicable to SOI or other substrates.
Claims
1. A semiconductor structure, comprising:
- a substrate having disposed thereon a silicon layer and a silicon germanium layer;
- an insulator disposed between the silicon layer and the silicon germanium layer;
- a silicon nitride film disposed conformally on the silicon layer and the silicon germanium layer; and
- a SiO2 layer disposed on the silicon nitride film.
2. The structure as claimed in claim 1 wherein the silicon germanium layer has a Ge concentration of approximately 20%.
3. The structure of claim 1 wherein said insulator has an upper most surface that is coplanar within an uppermost surface of each of said silicon layer and said silicon germanium layer.
4. The structure of claim 1 wherein said insulator has one vertical sidewall in direct physical contact with a vertical sidewall of said silicon layer and another vertical sidewall in direct physical contact with a vertical sidewall of said silicon germanium layer.
5. The structure of claim 1 wherein said substrate comprises bulk silicon.
6. The structure of claim 1 wherein said silicon germanium layer is present at a p-FET region of the substrate, and the silicon layer is present at an n-FET region of said substrate.
7. The structure of claim 1 wherein said silicon germanium layer consists essentially of silicon and germanium, and said silicon layer consists essentially of silicon.
8. The structure of claim 1 wherein said SiO2layer has a thickness that is greater than a thickness of said silicon nitride film.
9. The structure of claim 1 wherein an n-FET gate stack is present on a portion of said SiO2 layer that is located atop said silicon layer, and wherein a p-FET gate stack is present atop another portion of said SiO2layer that is located atop said silicon germanium layer, said n-FET gate stack is comprised of different materials that said p-FET gate stack.
10. The structure of claim 9 wherein said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, La2O3, TiN and polysilicon.
11. The structure of claim 10 wherein said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, TiN and polysilicon.
12. A semiconductor structure, comprising:
- a substrate having disposed thereon a silicon layer and a silicon germanium layer;
- an insulator disposed between the silicon layer and the silicon germanium layer; and
- a SiO2layer disposed on the silicon layer and the silicon germanium layer.
13. The structure as claimed in claim 12 wherein the silicon germanium layer has a Ge concentration of approximately 20%.
14. The structure of claim 12 wherein said insulator has an upper most surface that is coplanar within an uppermost surface of each of said silicon layer and said silicon germanium layer.
15. The structure of claim 12 wherein said insulator has one vertical sidewall in direct physical contact with a vertical sidewall of said silicon layer and another vertical sidewall in direct physical contact with a vertical sidewall of said silicon germanium layer.
16. The structure of claim 12 wherein said substrate comprises bulk silicon.
17. The structure of claim 12 wherein said silicon germanium layer is present at a p-FET region of the substrate, and the silicon layer is present at an n-FET region of said substrate.
18. The structure of claim 12 wherein said silicon germanium layer consists essentially of silicon and germanium, and said silicon layer consists essentially of silicon.
19. The structure of claim 12 wherein an n-FET gate stack is present on a portion of said SiO2 layer that is located atop said silicon layer, and wherein a p-FET gate stack is present atop another portion of said SiO2layer that is located atop said silicon germanium layer, said n-FET gate stack is comprised of different materials that said p-FET gate stack.
20. The structure of claim 9 wherein said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, La2O3, TiN and polysilicon, and said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, TiN and polysilicon.
Type: Application
Filed: Mar 27, 2012
Publication Date: Jul 26, 2012
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Joseph F. Shepard, JR. (Hopewell Junction, NY), Siddarth A. Krishnan (Hopewell Junction, NY), Rishikesh Krishnan (Hopewell Junction, NY), Michael P. Chudzik (Hopewell Junction, NY)
Application Number: 13/431,537
International Classification: H01L 27/092 (20060101);