ETCH STOP LAYER FORMATION IN METAL GATE PROCESS
A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
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This application is a continuation of U.S. patent application Ser. No. 13/449,433, filed Apr. 18, 2012 the entire content and disclosure of which is incorporated herein by reference.
BACKGROUNDThe present disclosure relates generally to semiconductor integrated circuits. More particularly, the present disclosure relates to scaling of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs). In order to be able to make integrated circuits, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as MOSFETs and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions of the device.
SUMMARYIn one embodiment, a semiconductor device is formed by a method that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate, wherein the metal gate conductor is comprised of a catalytic metal. A gate dielectric cap comprising at least silicon and oxygen is formed on the metal gate conductor. The gate dielectric cap is catalyzed by the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
In another aspect, a semiconductor device is provided that includes a gate structure on a channel portion of a semiconductor substrate. The gate structure includes at least one gate dielectric in contact with the channel portion of the semiconductor substrate and a gate conductor comprised of a catalytic metal. The at least one gate dielectric has a U-shaped geometry. A gate dielectric cap is present on the gate conductor, wherein the gate dielectric cap has edges that are substantially self-aligned to sidewalls of the gate conductor. The gate dielectric cap comprises at least silicon and oxygen and has a self-limited thickness of less than 20 nm. A source region and a drain region are present on opposing sides of the gate structure. A contact is present to each of the source region and the drain region. The contact is separated from the gate conductor by at least the gate conductor.
The following detailed description, given by way of example and not intended to limit the disclosure solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
Detailed embodiments of the methods and structures of the present disclosure are described herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the disclosed methods and structures that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the disclosure are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures, as they are oriented in the drawing figures.
It has been determined that one consequence of scaling semiconductor devices, such as field effect transistors (FETs), is that as the distance between adjacent semiconductor devices is decreased it is becomes increasingly difficult to form interconnects to the source region and the drain region without shorting the gate structures. In one aspect, the present disclosure provides a process sequence for manufacturing a semiconductor device that forms a dielectric gate cap atop a metal gate conductor composed of a catalytic metal, in which the catalytic metal functions as a catalyst to selective deposition of the dielectric material of the dielectric gate cap on only the metal gate conductor in a self-aligned manner. More specifically, by self-aligned it is meant that the deposited material of the dielectric gate cap is deposited continuously atop the entire upper surface of the metal gate conductor, wherein the edges of the dielectric gate cap are aligned to the sidewalls of the metal gate conductor. In one embodiment, the catalytic metal that dictates the self-aligned characteristics of the dielectric gate cap also provides that the dielectric gate cap has a self-limiting thickness.
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At least one dielectric gate spacer 15 may then be formed adjacent to the replacement gate structure 10, i.e., in direct contact with the sidewall of the replacement gate structure 10. In one embodiment, the at last one dielectric gate spacer 15 may be formed by using a blanket layer deposition, such as chemical vapor deposition, and an anisotropic etchback method. The at least one dielectric gate spacer 15 may have a width ranging from 2.0 nm to 15.0 nm, and may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof. The dielectric gate spacer 15 is optional, and may be omitted.
In some embodiments, a source region 20 and a drain region 25 may then be formed in the portions of the semiconductor substrate 5 that are present on opposing sides of replacement gate structure 10. In one embodiment, the source region 20 and the drain region 25 are formed using an ion implantation process. The conductivity type, e.g., n-type or p-type, of the source region 20 and the drain region 25 typically dictates the conductivity type of the semiconductor device, e.g., nFET or pFET. In a silicon-containing semiconductor substrate 5, examples of p-type dopants, i.e., impurities, include but are not limited to, boron, aluminum, gallium and indium, and examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.
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In one embodiment, the at least one gate dielectric 46 may be deposited by chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD). In one embodiment, the at least one gate dielectric 46 may be deposited using a conformal deposition method. The term “conformal” denotes a layer having a thickness that does not deviate from greater than or less than 20% of an average value for the thickness of the layer. In one embodiment, the thickness of the at least one gate dielectric 46 ranges from 0.8 nm to 6.0 nm. In one embodiment, the side cross-section of at least one gate dielectric 46 has a U-shaped geometry, as depicted in
The at least one metal gate conductor 47 is formed on the at least one gate dielectric 46. The at least one metal gate conductor 47 is composed of a catalytic metal. A “catalytic metal” is a metal that provides for a polymerization reaction with the precursor of the atomic layer deposition (ALD) half reaction for forming the gate dielectric cap that is self-aligned to the metal gate conductor. In one embodiment, the catalytic metal is a Lewis-acid type metal. As used herein, a “Lewis-acid type metal” is a metal ion that functions as an electron pair acceptor in the formation of a stable substance. Examples of catalytic metals include aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) and a combination thereof. The at least one metal gate conductor 47 may be formed by a deposition process, such as CVD, plasma-assisted CVD, plating, and/or sputtering, followed by planarization. More specifically, in one embodiment, the at least one metal gate conductor 47 may be deposited filling the opening produced by removing the replacement gate structure 10.
The gate dielectric cap 50 may be formed using an atomic layer deposition (ALD) half reaction. Atomic Layer Deposition (ALD) uses self-limiting surface reactions to deposit material layers in the monolayer or sub-monolayer thickness regime. ALD is similar in chemistry to chemical vapor deposition (CVD), except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction. The atomic layer depsoition (ALD) process of the present disclosure uses only half reactions to deposit the gate dielectric cap 50. The precusor of the atomic layer deposition process may be a silicon containing precursor. In some embodiments, the percursor may have the following chemical formulation:
In one embodiment, in which R in the above chemical formula is equal to an alkyloxy group, the precursor may be tris (tert-butyloxyl) silanol. In another embodiment, in which R in the above chemical formula is a butyl group, such as tert-butyl, the precursor may be at least one of bis(tert-butyloxyl) alkyl silanol, and mono-tert-butyloxyl alkyl silanol. Other butyl groups that are suitable for R in the above chemical formula include n-butyl, iso-butyl, and sec-butyl. It is noted that the above examples are provided for illustrative purposes only, as the R group in the above chemical formula for the precursor of the ALD half reaction may be any group having a carbon chain. For example, the R group in the above chemical formula may be an alkyl group, such as methyl group, ethyl group, propyl group, n-propyl group, isopropyl group, pentyl group, hexyl group, octyl group and combinations thereof.
In one example, in which the silicon precursor of the ALD half reaction process is tris (tert-butyloxyl) silanol, the deposited gate dielectric cap 50 is composed of silicon oxide (SiO2). In another example, in which the silicon precursor of the ALD half reaction process is bis(tert-butyloxyl) alkyl silanol, the deposited gate dielectric cap 50 is silicon-oxycarbide (SiCO). In another example, in which the silicon precursor of the ALD half reaction process is bis-tert-butyloxyl-aminoalkyl silanol, the gate dielectric cap 50 comprises silicon carbon nitro-oxide (SiCNO).
The ALD half reaction using one of the above described precursors is a self-aligned and self-limiting deposition process. For example, in some embodiments, the above described precursor gasses are chemisorbed by the catalytic metal of the at least one metal gate conductor 47, wherein the silanol molecules can then diffuse into the catalytic metal. Repeated insertion of the silanol molecules into the catalytic metal of the at least one metal gate conductor 47 form a siloxane polymer bound to the surface of the at least one metal gate conductor 47 through the catalytic metal, e.g., aluminum. This siloxane polymer is attached to the surface by strong chemical bonds and is thus non-volatile, i.e., a chemisorbed material. Because silanol can diffuse through this soft, surface bound siloxane polymer, the catalytic metal remains available to catalyze the polymerization of the silanol molecules. The self-aligned and rate-limiting mechanism in this process is the catalytic conversion of silanol to siloxane, provided that the concentration of silanol vapor is sufficiently high to keep the catalytic aluminum atoms fully occupied. In this case, the chemisorption rate does not depend on the rate at which silanol arrives at the surface of the siloxane layer. In the language of chemical kinetics, the chemisorption rate is zero order in the vapor concentration of silanol. The self aligned and self-limiting nature of the ALD half reaction results from cross-linking of the siloxane polymer.
More specifically, the cross-linking reactions connect the siloxane polymer chains, causing the polymer layer to gel and eventually solidify. For example, in the embodiments in which the precursor of the ALD half reaction is tris (tert-butyloxyl) silanol, the polymer layer may solidify to form silica (SiO2). In another example, in which the precursor of the ALD half reaction is bis(tert-butyloxyl) alkyl silanol, the polymer layer may solidify to form silicon-oxycarbide (SiCO). In yet another example, in which the precursor of the ALD half reaction is mono-tert-butyloxyl alkyl silanol, the polymer layer may solidify to form silicon carbon nitro-oxide (SiCNO). Because the silanol presumably has a negligible rate of diffusion through solid silica, silicon-oxycarbide (SiCO) or silicon carbon nitro-oxide (SiCNO), additional silanol can no longer reach the catalytic metal, e.g., aluminum, so the chemisorption stops, i.e., becomes self-limited. By “self-limiting” or “self-limited” it is meant that the amount of film material deposited in each reaction cycle of the ALD deposition is constant. One ALD half reaction may take from 0.5 seconds to a few seconds and may deposit a gate dielectric cap 50 having a self limited thickness between 1.0 nm and 20 nm. In another embodiment, the gate dielectric cap 50 has a self limited thickness that ranges from 1.0 nm to 10 nm. The self-limited thickness may be provided by one ALD half reaction cycle. Further details regarding one embodiment of the ALD half reaction process that provides the self-aligned and self-limited gate dielectric cap 50 may be found in Hausmann et al. “Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates”, Science, Vol. 498, p. 402 (Oct. 11, 2002).
Via openings may be formed to expose an upper surface of the source region 20 and the drain region 25. The via openings may be formed using photolithography and etch processes. For example, a photoresist etch mask can be produced by applying a photoresist layer to the upper surface of the second interlevel dielectric layer 55, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer. The photoresist etch mask may be positioned so that the portions of the second interlevel dielectric layer 55 that are not protected by the photoresist etch mask may be etched in order to provide the via openings. The exposed portion of the second interlevel dielectric layer 55 is then removed by a selective etch. The etch that removes the exposed portions of the second interlevel dielectric layer 55 is selective to at least the gate dielectric cap 50, and may also be selective to the dielectric spacers 15 and the semiconductor substrate 5. The etch that removes the exposed portion of the second interlevel dielectric layer 55 may be an anisotropic etch. Examples of anisotropic etch process suitable for forming the via openings include, but are not limited to, reactive-ion etching (RIE), ion beam etching, plasma etching and/or laser ablation. Contacts 60 may be formed in the via openings, in which the contacts 60 are in direct contact with the upper surface of the source region 20 and the drain region 25. Contacts 60 are formed by depositing a conductive metal into the via openings using a deposition process, such as physical vapor deposition (PVD), such as sputtering and plating. The contact 60 may be composed of conductive metals, such as titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, and alloys thereof. Following the formation of the contacts 60, a separate contact may be formed to the at least one metal gate conductor 47.
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While the claimed methods and structures has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the presently claimed methods and structures.
Claims
1. A semiconductor device comprising:
- a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric layer having a U-shaped geometry in contact with the channel portion of the semiconductor substrate and a metal gate conductor comprised of a catalytic metal;
- a gate dielectric cap having edges that are substantially self-aligned to sidewalls of the metal gate conductor, wherein the gate dielectric cap is an oxide-containing dielectric having a self-limited thickness of less than 20 nm;
- a source region and a drain region on opposing sides of the gate structure; and
- a contact to each of the source region and the drain region, wherein the contact is separated from the metal gate conductor by at least the gate dielectric cap.
2. The semiconductor device of claim 1, wherein the at least one gate dielectric layer is comprised of a high-k dielectric material.
3. The semiconductor device of claim 1, wherein the at least one gate dielectric layer has a thickness that ranges 0.8 mm to 6.0 mm.
4. The semiconductor device of claim 2, wherein the high-k dielectric material is selected from the group consisting of HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3 and mixtures thereof.
5. The semiconductor device of claim 1, wherein the gate dielectric cap comprises at least one of silicon-oxycarbide (SiCO), silicon carbon nitro-oxide (SiCNO) and silicon oxide (SiO2).
6. The semiconductor device of claim 1, wherein the catalytic metal comprises aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) or a combination thereof.
7. The semiconductor device of claim 1, wherein a spacer is adjacent to the gate structure.
8. The semiconductor device of claim 4, wherein said edges of the gate dielectric cap that are substantially self-aligned to sidewalls of the metal gate conductor may extend past the metal gate conductor over the spacer by a dimension of 20 nm or less.
9. The semiconductor device of claim 1, wherein the gate structure of the semiconductor device and an adjacent gate structure of an adjacent semiconductor device are separated by a pitch ranging from 30 nm to 100 nm.
10. The semiconductor device of claim 1 further comprising dielectric spacers adjacent to the gate structure, wherein the material of the gate dielectric cap is not present on an exterior surface of the dielectric spacers.
11. The semiconductor device of claim 1, wherein the catalytic metal is aluminum, the interface oxide is aluminum oxide (Al2O3), and the gate dielectric cap is silicon oxide (SiO2).
12. The semiconductor device of claim 1, wherein at least one contact of said contact to each of the source region and the drain region is in direct contact with the gate dielectric cap.
13. The semiconductor device of claim 1, wherein the at least one contact is comprised of titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, or alloys thereof.
Type: Application
Filed: Feb 28, 2013
Publication Date: Oct 24, 2013
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Zhengwen Li (Danbury, CT), Michael P. Chudzik (Danbury, CT), Ramachandra Divakaruni (Ossining, NY), Siddarth A. Krishnan (Peekskill, NY), Unoh Kwon (Fishkill, NY), Richard S. Wise (Newburgh, NY)
Application Number: 13/780,957
International Classification: H01L 29/51 (20060101);