Patents by Inventor Siegfried Schwarzl

Siegfried Schwarzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050054184
    Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 10, 2005
    Inventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
  • Patent number: 6849365
    Abstract: A reflection mask has a multilayer reflection layer for the reflection of radiated-in radiation by constructive interference of the reflected partial beams and a multilayer layer, whose periodicity effects a destructive interference of the reflected partial beams and which performs the function of an absorber. One of the two multilayer layers is patterned in accordance with a structure to be imaged.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: February 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Siegfried Schwarzl, Stefan Wurm
  • Patent number: 6825098
    Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: November 30, 2004
    Assignee: Infineon Technologies AG
    Inventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
  • Publication number: 20040218441
    Abstract: In the memory cell array of a semiconductor memory the memory elements or memory cells with a magnetoresistive effect can have a hard-magnetic memory layer and a soft-magnetic sensor layer. The magnetization axis of the hard-magnetic layer lies parallel to the line connected thereto, and the magnetization axis lies parallel to the line connected thereto. By an AC voltage or AC current source, a voltage or current signal is impressed on a respective selected line. The magnetization direction of the soft-magnetic layer is sinusoidally deflected from the easy magnetization axis. In addition to the impressed signal, the magnetoresistive resistance of the memory cell also changes as a result. Depending on the magnetization direction of the hard-magnetic layer, the signal is modulated in-phase or in-antiphase by the variable resistance. The sign supplies the memory information.
    Type: Application
    Filed: April 2, 2004
    Publication date: November 4, 2004
    Inventor: Siegfried Schwarzl
  • Publication number: 20040115563
    Abstract: A radiation-sensitive coating material, in addition to a base polymer, has a solvent and a radiation-active substance which forms an acid on irradiation by light (including energetic electrons or ions), a fluorescent substance which alters its fluorescence property subject to a change in the acid content of its surroundings. In a process for exposing a substrate coated with the coating material at least one sensor in the exposure chamber of the exposure apparatus measures the intensity of the change in fluorescence spectrum as a function of time during the exposure operation. From the course of intensity at the time of an individual line of the fluorescence spectrum or the intensity integrated over a wavelength interval it is possible to determine the endpoint of the exposure operation by way of electronic algorithms. Deviations from experimentally determined ideal curves of the intensity course provide information on erroneous functions in the course of coating material application and exposure.
    Type: Application
    Filed: September 29, 2003
    Publication date: June 17, 2004
    Inventors: Jenspeter Rau, Siegfried Schwarzl, Stefan Wurm
  • Publication number: 20040092093
    Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.
    Type: Application
    Filed: September 3, 2003
    Publication date: May 13, 2004
    Inventors: Siegfried Schwarzl, Manfred Engelhardt, Franz Kreupl
  • Publication number: 20040084749
    Abstract: A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 6, 2004
    Inventors: Werner Pamler, Siegfried Schwarzl, Zvonimir Gabric
  • Patent number: 6717843
    Abstract: A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage cells, each storage cell having two intersecting electric conductors and a layer system comprising magnetic layers located at the intersection of the electric conductors. The memory is characterized in that the layer system is designated as a multilayer system with two or more magnetic layers, wherein at least two of the magnetic layers have a magnetization direction that can be set independently of one another. Further, the magnetization direction of the individual layers may be changed on the basis of the electric current flowing through the electric conductors.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: April 6, 2004
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Werner Weber, Siegfried Schwarzl
  • Publication number: 20040033652
    Abstract: A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.
    Type: Application
    Filed: June 25, 2003
    Publication date: February 19, 2004
    Inventors: Zvonimir Gabric, Werner Pamler, Siegfried Schwarzl
  • Patent number: 6686643
    Abstract: Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is disposed in the first insulating layer and is covered by the second insulating layer. The cavities and the metal structures are produced next to one another by self-aligned process steps.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: February 3, 2004
    Assignee: Infineon Technologies AG
    Inventors: Siegfried Schwarzl, Werner Pamler, Zvonimir Gabric
  • Publication number: 20040004884
    Abstract: Memory cell arrangement having a memory cell array which has at least one layer of magnetoresistive memory components (11) which are each connected to first contact-making lines (10), the first contact-making lines (10) lying within a first dielectric layer (6), and are each connected to second contact-making lines (20; 29; 35), the second contact-making lines (20; 29; 35) lying within a second dielectric layer (17; 27; 32).
    Type: Application
    Filed: July 31, 2003
    Publication date: January 8, 2004
    Inventors: Stefan Miethaner, Siegfried Schwarzl, Annette Saenger
  • Publication number: 20030232256
    Abstract: A photolithographic mask for patterning a photosensitive material, in particular on a wafer, has at least one structure region for imaging a structure on the photosensitive material, and an absorber structure for absorbing incident radiation. At least one structure region is provided and has at least one protective layer made of chemically and mechanically resistive material. In this way, the photolithographic mask can be cleaned chemically and/or mechanically, without the structure regions being attacked and damaged by the chemical and/or mechanical cleaning media. Furthermore, a plurality of methods are possible for fabricating a photolithographic mask of this type.
    Type: Application
    Filed: May 21, 2003
    Publication date: December 18, 2003
    Inventors: Stefan Wurm, Siegfried Schwarzl
  • Patent number: 6630703
    Abstract: A storage cell configuration including magnetoresistive storage elements located in a cell field between first lines and second lines. A first metalization plane, a second metalization plane and contacts connecting the first metalization plane to the second metalization plane are provided in a periphery. The first lines and the first metalization plane and the second lines and the contacts are disposed on the same plane respectively so that they can be produced by structuring one conductive layer respectively.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: October 7, 2003
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Scheler, Siegfried Schwarzl
  • Patent number: 6605837
    Abstract: A memory cell configuration includes a magnetoresistive element with an annular cross-section in a layer plane, a first line and a second line. The first and second lines crossing each other. The magnetoresistive element is disposed in the crossing region between the first line and the second line. The first line and/or the second line include at least one first portion, in which the predominant current component is oriented parallel to the layer plane, and one second portion, in which the predominant current component is oriented perpendicular to the layer plane.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: August 12, 2003
    Assignee: Infineon Technologies AG
    Inventor: Siegfried Schwarzl
  • Patent number: 6579729
    Abstract: Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of a respective one of the layers run parallel to one another. The metallic lines of mutually adjacent layers run transversely with respect to one another.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: June 17, 2003
    Assignee: Infineon Technologies AG
    Inventors: Bernd Goebel, Siegfried Schwarzl
  • Patent number: 6577526
    Abstract: The magnetoresistive element has a first ferromagnetic element, a nonmagnetic layer element, and a second ferromagnetic layer element arranged in such a way that the nonmagnetic layer element is disposed between the first ferromagnetic layer element and the second ferromagnetic layer element. The first ferromagnetic layer element and the second ferromagnetic layer element are formed of substantially the same material, but they differ in their extent parallel to the interface to the nonmagnetic layer element in that they have different measurements in at least one dimension. The magnetoresistive element is suitable both as a sensor element and as a memory element in a memory cell configuration.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: June 10, 2003
    Assignee: Infineon Technologies AG
    Inventor: Siegfried Schwarzl
  • Patent number: 6574138
    Abstract: A memory cell configuration has memory cells that each contain two magnetoresistive elements. If the two magnetoresistive elements of each memory cell are magnetized in such a way that they have different resistances, the information stored in the memory cell can be determined with a resistor half-bridge circuit by assessing whether the signal tapped off at the output is greater than or less than zero.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: June 3, 2003
    Assignee: Infineon Technologies AG
    Inventors: Siegfried Schwarzl, Stefan Miethaner
  • Publication number: 20030091910
    Abstract: A reflection mask has a multilayer reflection layer for the reflection of radiated-in radiation by constructive interference of the reflected partial beams and a multilayer layer, whose periodicity effects a destructive interference of the reflected partial beams and which performs the function of an absorber. One of the two multilayer layers is patterned in accordance with a structure to be imaged.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 15, 2003
    Inventors: Siegfried Schwarzl, Stefan Wurm
  • Patent number: 6510078
    Abstract: In a storage cell array, a first and a second line are provided which have a crossing point, at which a storage element with magnetoresistive effect is disposed. A yoke is provided which surrounds one of the lines and that contains magnetizable material with a permeability of at least 10. The yoke is disposed in such a way that a magnetic flow is closed substantially through the storage element.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: January 21, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventor: Siegfried Schwarzl
  • Publication number: 20020192571
    Abstract: A method for fabricating a lithographic reflection mask in particular for patterning of semiconductor wafers, is described, and can be used for extremely small feature sizes below 100 nm. In known lithographic methods with EUV radiation (extreme ultraviolet), for the mask fabrication, a multilayer reflection layer is applied to a substrate. An absorber layer is deposited after the multilayer layer is patterned above the multilayer layer or is completely introduced into the latter. In the case of the method according to the invention, in contrast, the absorber layer is applied between the substrate and the reflection layer and/or on the side areas of the reflection layer. This has the advantage of reducing CD changes due to shadowing of structures lying above the reflection layer. Further advantages are, inter alia, smaller structure displacements and reduced asymmetrical intensity profiles of the reflected beams of radiation.
    Type: Application
    Filed: May 16, 2002
    Publication date: December 19, 2002
    Inventor: Siegfried Schwarzl