Abstract: A method used in manufacturing a cubically integrated circuit arrangement. A silicon wafer, wherein through pores are produced by electrochemical etching are insulated from the silicon wafer, and are provided with conductive fills, is secured as a carrier plate (24) to a substrate (21) that has components and that is integrated in a cubically integrated circuit arrangement. Terminal pads (25) that are electrically connected to conductive fills and that are arranged on the surface of the carrier plate (24) thereby meet contacts (23) to the components that are arranged at the surface of the substrate (21) adjoining the carrier plate (24) and that are firmly connected thereto.

Abstract: A trench mask containing SiO.sub.2 is produced on a substrate (1) of single-crystal silicon. After deposition of a first Si.sub.3 N.sub.4 layer, first Si.sub.3 N.sub.4 spacers (31) are formed by anisotropic etching, and a first trench is etched to a first depth (t.sub.1). After selective removal of passivation layers arising in the first trench etching and after deposition of a second Si.sub.3 N.sub.4 layer, second Si.sub.3 N.sub.4 spacers (41) are formed by anisotropic etching. A second trench is etched to a second depth (t.sub.2), whereby the trench structure (5) is formed to a total depth (t.sub.1 and t.sub.2).

Abstract: A method for the manufacture of bipolar transistor structures with self-adjusted emitter and base regions wherein the emitter and base regions are generated by an out-diffusion from doped polysilicon layers. Dry etching processes which produce vertical etching profiles are employed for structuring the SiO.sub.2 and polysilicon layers. The employment of additional oxidation processes for broadening the lateral edge insulation (see arrow 9) during the manufacture of the bipolar transistor structures enables self-adjusted emitter-base structures with high reproducibility in addition to advantages with respect to the electrical parameters. The method is employed for the manufacture of VLSI circuits in bipolar technology.