Abstract: Tamper-proof electronic packages and fabrication methods are provided which include a glass substrate. The glass substrate is stressed glass with a compressively-stressed surface layer. Further, one or more electronic components are secured to the glass substrate within a secure volume of the tamper-proof electronic package. In operation, the glass substrate is configured to fragment with an attempted intrusion event into the electronic package, and the fragmenting of the glass substrate also fragments the electronic component(s) secured to the glass substrate, thereby destroying the electronic component(s). In certain implementations, the glass substrate has undergone ion-exchange processing to provide the stressed glass.

Abstract: Tamper-proof electronic packages and fabrication methods are provided which include a glass enclosure enclosing, at least in part, at least one electronic component within a secure volume, and a tamper-respondent detector. The glass enclosure includes stressed glass with a compressively-stressed surface layer, and the tamper-respondent detector monitors, at least in part, the stressed glass to facilitate defining the secure volume. The stressed glass fragments with an attempted intrusion event through the stressed glass, and the tamper-respondent detector detects the fragmenting of the stressed glass. In certain embodiments, the stressed glass may be a machined glass enclosure that has undergone ion-exchange processing, and the compressively-stressed surface layer of the stressed glass may be compressively-stressed to ensure that the stressed glass fragments into glass particles of fragmentation size less than 1000 ?m with the intrusion event.

Abstract: One or more embodiments may provide the capability to enumerate maximal cliques of graph data by constructing and traversing a search tree through a single sequential pass on an adjacency list. The adjacency list may be generated so as to enable the at least one maximal clique to be generated in one single sequential pass.

Abstract: Embodiments are directed to an IC device comprising a set of N elements, and an interconnect system for enabling communication between the set of elements. Each element of the set of elements is configured according to a first communication plan to receive attestation data of each other element of the set of elements. Upon receiving the attestation data the element may determine whether each of the received attestation data from the other elements match an attestation pattern as defined in the first communication plan. In case the received attestation data match the first communication plan, the element may determine whether the received attestation data is attested by N?1 elements of the set of elements. In case the attestation data is attested by N?1 elements of the set of elements, the element may indicate the presence of the set of elements before the time interval has lapsed.

Abstract: An iterative refinement apparatus configured to generate data defining a solution vector x for a linear system represented by Ax=b, where A is a predetermined matrix and b is a predetermined vector. An outer solver processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is configured to process said data items having variable bit-width and data format. A precision controller determines the bit-widths and data formats of the data items adaptively in dependence on the results of the processing steps of the iterative refinement method; the precision controller configured to control operation of the inner solver for processing said data items with the bit-widths and data formats.

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure to circuit board protection. The tamper-respondent assemblies include a circuit board, and an electronic enclosure mounted to the circuit board and facilitating enclosing at least one electronic component within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and the tamper-respondent electronic circuit structure includes a tamper-respondent circuit. An adhesive is provided to secure, in part, the electronic enclosure to the circuit board. The adhesive contacts, at least in part, the tamper-respondent circuit so that an attempted separation of the electronic enclosure from the circuit board causes the adhesive to break the tamper-respondent circuit, facilitating detection of the separation by a monitor circuit of the tamper-respondent electronic circuit structure.

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure to circuit board protection. The tamper-respondent assemblies include a circuit board, and an electronic enclosure mounted to the circuit board and facilitating enclosing at least one electronic component within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and the tamper-respondent electronic circuit structure includes a tamper-respondent circuit. An adhesive is provided to secure, in part, the electronic enclosure to the circuit board. The adhesive contacts, at least in part, the tamper-respondent circuit so that an attempted separation of the electronic enclosure from the circuit board causes the adhesive to break the tamper-respondent circuit, facilitating detection of the separation by a monitor circuit of the tamper-respondent electronic circuit structure.

Abstract: A method is provided for searching a graph to identify cliques using a set of processing elements (PEs), a first PE of the set of PEs having access to an adjacency list of a seed vertex of the graph, the adjacency list of the seed vertex including a set of vertices. The method includes: generating a data structure for each intermediate vertex of the set of vertices, the data structure indicating the respective intermediate vertex and an additional list of intermediate vertices of the set of vertices; storing the generated data structures; for each buffered data structure, receiving the buffered data structure and configuring the available PE to receive an adjacency list of the intermediate vertex indicated in the respective data structure and to select from the adjacency list a set of further vertices that are adjacent to the seed vertex and are part of the additional list.

Abstract: Embodiments of the present invention may involve providing security to a computing device. The providing security to a computing device may involve performing crypto-operations. A security system may include a central processing unit and a pre-processing unit. The pre-processing unit may be configured for receiving an incoming encapsulated request, parsing header infrastructure information of the encapsulated request, decapsulating the request, and providing the decapsulated request to the central processing unit for further processing.

Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: A conjugate gradient solver apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax=b where A is a predetermined matrix and b is a predetermined vector. The apparatus includes solver circuitry and a precision controller. The solver circuitry processes input data, defining said matrix A and vector b, in accordance with an iterative conjugate gradient method to generate said data defining the solution vector x. The solver circuitry is adapted to process data items, corresponding to vectors used in said conjugate gradient method, having a variable fixed-point data format. The precision controller determines the fixed-point data formats of respective said data items adaptively during progress of the conjugate gradient method in the solver circuitry.

Abstract: A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.

Abstract: A conjugate gradient solver apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax=b where A is a predetermined matrix and b is a predetermined vector. The apparatus includes solver circuitry and a precision controller. The solver circuitry processes input data, defining said matrix A and vector b, in accordance with an iterative conjugate gradient method to generate said data defining the solution vector x. The solver circuitry is adapted to process data items, corresponding to vectors used in said conjugate gradient method, having a variable fixed-point data format. The precision controller determines the fixed-point data formats of respective said data items adaptively during progress of the conjugate gradient method in the solver circuitry.

Abstract: A device for matching, in input data, a regular expression with back-references, represented by a finite-state machine (FSM). The device comprises a plurality of parallel processing elements (PPEs), an interconnection network for interconnecting the PPEs with each other, and a memory for receiving and storing input data. The PPEs process the input data stored in the memory, based on backtracking to process the back-references, and implement FA next state logic to generate new active FA configurations or mark themselves as available to receive active FA configurations. The interconnection network retrieves active FA configurations from the PPEs and allocates the active FA configurations to available PPEs. The PPEs are configured to match a regular expression in the input data.

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure to circuit board protection. The tamper-respondent assemblies include a circuit board, and an electronic enclosure mounted to the circuit board and facilitating enclosing at least one electronic component within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and the tamper-respondent electronic circuit structure includes a tamper-respondent circuit. An adhesive is provided to secure, in part, the electronic enclosure to the circuit board. The adhesive contacts, at least in part, the tamper-respondent circuit so that an attempted separation of the electronic enclosure from the circuit board causes the adhesive to break the tamper-respondent circuit, facilitating detection of the separation by a monitor circuit of the tamper-respondent electronic circuit structure.

Abstract: A circuitized structure with a 3-dimensional configuration. A base structure is provided that includes an insulating substrate of electrically insulating material with a flat configuration, and further includes an electric circuit including at least one layer of electrically conductive material arranged on the insulating substrate. The insulating material includes a thermosetting material being partially cured by stopping a cure thereof at a B-stage before reaching a gel point. The base structure is formed according to the 3-dimensional configuration, and the cure of the thermosetting material is completed.

Abstract: A circuitized structure with a 3-dimensional configuration. A base structure is provided that includes an insulating substrate of electrically insulating material with a flat configuration, and further includes an electric circuit including at least one layer of electrically conductive material arranged on the insulating substrate. The insulating material includes a thermosetting material being partially cured by stopping a cure thereof at a B-stage before reaching a gel point. The base structure is formed according to the 3-dimensional configuration, and the cure of the thermosetting material is completed.

Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.

Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.