Abstract: Methods and compositions for generating haploid organisms are described.

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract: Some embodiments of the present invention comprise an off-set gear assembly for use in producing cushioning material and methods for using the same. Each gear of the off-set gear assembly has at least two sections. Each section includes a set of gear teeth. The gear teeth of the two sections can be rotationally off-set and this can result in the production of cushioning material with staggered ridges. Some embodiments of the present invention also comprising cushioning material with staggered ridges.

Abstract: A putter-type golf club comprising an alignment system and a club head assembly. The putter-type club head has a body that is preferably composed of aluminum, with a rear weight disc and small inserts composed of a material denser than the material used for the remainder of the club head (excluding inserts in the “wings” on the club head and/or neck of the club). The body has an alignment channel that is approximately the same width as a standard golf ball, and which runs from the face to the rear of the club head. In a preferred embodiment this alignment channel is black or dark in colour with a white or light-coloured border. The putter-type club has a neck that is inserted laterally through the side of the club head, such that it runs parallel to the face of the club head and for substantially the length of the face.

Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

Abstract: A putter-type golf club comprising an alignment system and a club head assembly. The putter-type club head has a body that is preferably composed of aluminium, with a rear weight disc and small inserts composed of a material denser than the material used for the remainder of the club head (excluding inserts in the “wings” on the club head and/or the neck of the club). The body has an alignment channel that is approximately the same width as a standard golf ball, and which runs from the face to the rear of the club head. In a preferred embodiment this alignment channel is black or dark in colour with a white or light-coloured border. The putter-type club has a neck that is inserted laterally through the side of the club head, such that it runs parallel to the face of the club head and for substantially the length of the face.

Abstract: The present invention provides for a brake actuator for use in a motor vehicle. In a motor vehicle with one or more brakes activated by a cable system, there is a lever, a pawl resiliently biased to engage a sector, and a cam member. Connected to the cam member is a cable that can tension and release the pawl by movement of a button that is slidably engaged with the cam member.

Abstract: A brake actuator comprising: a mount including an input lever, a pivotal shaft; an operative output member connected to the shaft, a connector arm positioned adjacent the input lever and spaced axially from the output member; and an adjustable connection device, comprising: a link; a first connector connecting the link to the input lever, wherein the first connector comprises a seat provided on the input lever and supporting the link and a seat support structure between the input lever and the seat for supporting the seat; and a second connector connecting the link to the connector arm; to connect the input lever to the connector arm and the shaft via the link such that, when the output member is connected to one or more cables, movement of the input lever in either the applying or releasing directions pivots the shaft to apply or release tension to the cables.

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: A method of controlling the state of polarization of an optical signal includes injecting the optical signal into a laser diode and matching the wavelength of the optical signal to a longitudinal mode of the laser diode. A stabilizer signal can also be injected in to the laser diode. The wavelength of the stabilizer signal is matched a first longitudinal mode of the laser diode a longitudinal mode of the laser diode to the optical signal.

Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a suicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Abstract: A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

Abstract: A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.