Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266047
    Abstract: Methods and intersection testing modules are provided for determining, in a ray tracing system, whether a ray intersects a 3D axis-aligned box representing a volume defined by a front-facing plane and a back-facing plane for each dimension. The front-facing plane of the box which intersects the ray furthest along the ray is identified. It is determined whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions, and this determination is used to determine whether the ray intersects the axis-aligned box. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: April 1, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Gregory Clark, Simon Fenney
  • Publication number: 20250097442
    Abstract: Compressed image data is received in substantially in raster scan order, and for each group of pixels in a row of the compressed image data, a block-based decoding scheme for the group of pixels is identified and the compressed data corresponding to the group of pixels is decoded at decoding hardware using the identified scheme.
    Type: Application
    Filed: November 30, 2024
    Publication date: March 20, 2025
    Inventors: Jeffery Thomas Bond, Gregory Alan Clark, Selina Hopton, Simon Fenney
  • Publication number: 20250095298
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Application
    Filed: November 30, 2024
    Publication date: March 20, 2025
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Publication number: 20250086252
    Abstract: Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. mobile devices) which have limited processing resources. At each of a set of predetermined interpolation positions within an array of data points, a set of predetermined weights represent a bicubic interpolation which can be applied to the data points. For a plurality of the predetermined interpolation positions which surround the sampling position, the corresponding sets of predetermined weights and the data points are used to determine a plurality of surrounding interpolated values which represent results of performing the bicubic interpolation at the surrounding predetermined interpolation positions.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Inventor: Simon Fenney
  • Patent number: 12236518
    Abstract: A hierarchical acceleration structure for use in a ray tracing system. When generating a node for the hierarchical acceleration structure, the primitives in a particular portion of the 3D scene may be alternatively bounded by different shaped volumes. These bounding volumes or ‘bounding regions’ can be Axis Aligned Bounding Boxes (AABBs), although other bounding volumes can be used. The ray tracing system may use sets of two or more bounding volumes in a 3D scene to bound all the primitives within that portion. The choice of how to create sets of multiple bounding volumes within a portion of the 3D scene may be done by using a binary space partition (BSP). Different sets of bounding regions may present different amounts of surface area for a hypothetical ray entering the portion of the 3D scene dependent upon the expected ray direction or angle.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: February 25, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Gregory Clark, Joseph John Davison
  • Publication number: 20250062776
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20250037349
    Abstract: A method and an intersection testing module in a ray tracing system for performing intersection testing for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. For each edge of a convex polygon defined by two of the projected vertices, a signed parameter is determined, wherein the sign of the signed parameter is indicative of which side of the edge the ray passes on. If the ray is determined to intersect a point on the edge then the sign of the signed parameter is determined using a module which is configured to: take as inputs, indications which classify each of pi, qi, pj and qj coordinates as negative, zero or positive, and output, for valid combinations of classifications of the pi, qi, pj and qj coordinates, an indication of the sign of the signed parameter.
    Type: Application
    Filed: October 7, 2024
    Publication date: January 30, 2025
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Patent number: 12211135
    Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y .
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: January 28, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Publication number: 20250022228
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Application
    Filed: July 30, 2024
    Publication date: January 16, 2025
    Inventor: Simon Fenney
  • Patent number: 12189711
    Abstract: Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. mobile devices) which have limited processing resources. At each of a set of predetermined interpolation positions within an array of data points, a set of predetermined weights represent a bicubic interpolation which can be applied to the data points. For a plurality of the predetermined interpolation positions which surround the sampling position, the corresponding sets of predetermined weights and the data points are used to determine a plurality of surrounding interpolated values which represent results of performing the bicubic interpolation at the surrounding predetermined interpolation positions.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: January 7, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20240428503
    Abstract: A method for grouping primitives into pairs of adjoining triangles for use in a ray tracing process. An input list of edges of triangular primitives is obtained, an edge bounding volume surface area (BVSA) and an additional edge qualifier is determined for each of the edges. The entries in the input list are sorted by edge BVSA then by edge qualifier, giving a sorted list in which the entries have a sorted order. The list is traversed in the sorted order to seek groups of matched edges within a predetermined window of list entries, each edge in a matched group having a matching edge BVSA and edge qualifier with another edge in the matched group from a different triangular primitive. When a group of matched edges is found, associated triangular primitives are designated as a cluster of adjoining primitives. The cluster of adjoining primitives are processed together as a group.
    Type: Application
    Filed: May 20, 2024
    Publication date: December 26, 2024
    Inventors: Aytek Aman, Simon Fenney
  • Patent number: 12170534
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: December 17, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20240406462
    Abstract: A method of compressing a set of image value data items each representing a position in image-value space so as to define an occupied region thereof. A series of compression transforms is applied to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. A set of one or more reference data items is identified that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the reference data items. Each image data item is encoded as a representation of the identified sequence of decompression transforms for that image data item. The data items and the decompression transforms are stored as compressed image data.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Inventor: Simon Fenney
  • Patent number: 12159350
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: December 3, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Patent number: 12160597
    Abstract: A method of data decompression includes receiving compressed pixel data substantially in raster scan order and determining a number of bits of compressed data that corresponds to one row of pixels. Then, for each group of pixels in the row, the method identifies a block-based decoding scheme for the group of pixels and decodes the group of pixels using the identified scheme.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: December 3, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Jeffery Thomas Bond, Gregory Alan Clark, Selina Hopton, Simon Fenney
  • Publication number: 20240394978
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 12112421
    Abstract: A method and an intersection testing module in a ray tracing system for performing intersection testing for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. For each edge of a convex polygon defined by two of the projected vertices, a signed parameter is determined, wherein the sign of the signed parameter is indicative of which side of the edge the ray passes on. If the ray is determined to intersect a point on the edge then the sign of the signed parameter is determined using a module which is configured to: take as inputs, indications which classify each of pi, qi, pj and qj coordinates as negative, zero or positive, and output, for valid combinations of classifications of the pi, qi, pj and qj coordinates, an indication of the sign of the signed parameter.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: October 8, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Peter Smith-Lacey, Rostam King, Gregory Clark, Simon Fenney
  • Publication number: 20240319963
    Abstract: A binary logic circuit and method for rounding an unsigned normalised n-bit binary number to an m-bit binary number. A correction value of length of n bits and a pre-truncation value of length of n bits are determined. The correction value is determined by shifting the n-bit number by m bits. The pre-truncation value is determined based on at least the n-bit number, the correction value, a value for the most significant bit (MSB) of the n-bit number, and a rounding value having a ‘1’ at the n?mth bit position and a ‘0’ at all other bits. The rounded m-bit number is then obtained by truncating the n?m least significant bits (LSB) of the pre-truncation value.
    Type: Application
    Filed: February 19, 2024
    Publication date: September 26, 2024
    Inventors: Rostam King, Simon Fenney
  • Publication number: 20240314323
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Publication number: 20240314291
    Abstract: A block of image data having a plurality of image element values each having a plurality of data values relating to a respective plurality of channels is compressed, wherein the channels comprise a reference channel and non-reference channels.
    Type: Application
    Filed: December 7, 2023
    Publication date: September 19, 2024
    Inventors: Ilaria Martinelli, Simon Fenney, Kellie Marks, Paul Higginbottom