Patents by Inventor Simon Fenney
Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12764346Abstract: A method of compressing a set of image value data items each representing a position in image-value space so as to define an occupied region thereof. A series of compression transforms is applied to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. A set of one or more reference data items is identified that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the reference data items. Each image data item is encoded as a representation of the identified sequence of decompression transforms for that image data item. The data items and the decompression transforms are stored as compressed image data.Type: GrantFiled: August 9, 2024Date of Patent: October 13, 2026Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 12750067Abstract: A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory.Type: GrantFiled: December 31, 2023Date of Patent: September 29, 2026Assignee: Imagination Technologies LimitedInventors: Simon Fenney, Greg Clark, Alan Vines
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Publication number: 20260278939Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.Type: ApplicationFiled: May 13, 2026Publication date: September 17, 2026Inventors: Peter Malcolm Lacey, Simon Fenney
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Publication number: 20260268528Abstract: A block of sub-primitive presence indications for use in intersection testing in a rendering system is compressed into a block of compressed data. Spatial decorrelation is performed to determine spatially decorrelated presence indications by (i) determining a predicted value for the presence indication based on one or more other presence indications in the line, and (ii) replacing the presence indication with a value of a difference between the presence indication and the determined predicted value for the presence indication. For each line of presence indications in a second dimension within the block, for one or more of the presence indications in the line: (i) a predicted value for the presence indication is determined based on one or more other presence indications in the line, and (ii) the presence indication is replaced with a value of a difference between the presence indication and the determined predicted value for the presence indication.Type: ApplicationFiled: April 30, 2026Publication date: September 10, 2026Inventor: Simon Fenney
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Publication number: 20260245290Abstract: A computer implemented method converts ray data for a ray into a ray representative, wherein the ray representative is a compressed representation of the ray data, and wherein the ray data comprises three direction components and three position components for the ray. The method comprises identifying which of the three direction components of the ray data has the greatest magnitude, and defining the axis of the identified direction component as the major axis of the ray. The method further comprises determining a translated position on the ray at which the position component along the major axis is zero, and rescaling the three direction components of the ray so that the magnitude of the direction component along the major axis is one. The ray representative comprises: (i) the two position components of the translated position along the axes which are not the major axis, and (ii) the two rescaled direction components along the axes which are not the major axis.Type: ApplicationFiled: April 10, 2026Publication date: August 20, 2026Inventors: Peter Smith-Lacey, Simon Fenney
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Publication number: 20260238230Abstract: A computer-implemented method of compressing a set of values, the method comprising: determining a matrix comprising the set of values; assessing a similarity between pairs of rows and/or pairs of columns of the matrix; reordering the rows and/or columns of the matrix in dependence on the similarity between the pairs of rows and/or pairs of columns so as to form a plurality of groups of values of the set of values; and compressing at least one group of values of the plurality of groups of values so as to compress the set of values.Type: ApplicationFiled: December 19, 2025Publication date: August 13, 2026Inventors: Gunduz Vehbi Demirci, Timothy James Atherton, James Stuart Imber, Simon Fenney
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Patent number: 12682556Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.Type: GrantFiled: May 23, 2023Date of Patent: July 14, 2026Assignee: Imagination Technologies LimitedInventors: Xile Yang, John W. Howson, Simon Fenney
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Publication number: 20260197014Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.Type: ApplicationFiled: March 2, 2026Publication date: July 9, 2026Inventor: Simon Fenney
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Patent number: 12657827Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.Type: GrantFiled: July 30, 2024Date of Patent: June 16, 2026Assignee: Imagination Technologies LimitedInventors: Peter Malcolm Lacey, Simon Fenney
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Patent number: 12646217Abstract: A block of sub-primitive presence indications for use in intersection testing in a rendering system is compressed into a block of compressed data. Spatial decorrelation is performed to determine spatially decorrelated presence indications by (i) determining a predicted value for the presence indication based on one or more other presence indications in the line, and (ii) replacing the presence indication with a value of a difference between the presence indication and the determined predicted value for the presence indication. For each line of presence indications in a second dimension within the block, for one or more of the presence indications in the line: (i) a predicted value for the presence indication is determined based on one or more other presence indications in the line, and (ii) the presence indication is replaced with a value of a difference between the presence indication and the determined predicted value for the presence indication.Type: GrantFiled: May 30, 2023Date of Patent: June 2, 2026Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Publication number: 20260141614Abstract: A computer-implemented method of performing intersection testing in a ray tracing system performs intersection testing for each of a plurality of rays against nodes of a hierarchical acceleration structure. The intersection testing for each of the rays comprises, in response to identifying, in a memory, an indication of a re-entry point associated with a ray identifier that is associated with the ray, fetching from the memory the indication of the re-entry point that is associated with the ray identifier, the re-entry point being a node of the hierarchical acceleration structure for which an intersection has been identified for a previously tested ray associated with the ray identifier. The intersection testing for each of the rays further comprises performing intersection testing of the ray against a set of nodes of the hierarchical acceleration structure starting from the re-entry point.Type: ApplicationFiled: January 14, 2026Publication date: May 21, 2026Inventors: Peter Smith-Lacey, Simon Fenney
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Patent number: 12625920Abstract: An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by at least one polynomial function. At least one control point representing the polynomial function is retrieved from at least one look up table, and the polynomial function can be derived from the control points. The function is evaluated at the input value and an output of the evaluation is used as a value of the function at that input value.Type: GrantFiled: January 27, 2022Date of Patent: May 12, 2026Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 12620161Abstract: A computer implemented method converts ray data for a ray into a ray representative, wherein the ray representative is a compressed representation of the ray data, and wherein the ray data comprises three direction components and three position components for the ray. The method comprises identifying which of the three direction components of the ray data has the greatest magnitude, and defining the axis of the identified direction component as the major axis of the ray. The method further comprises determining a translated position on the ray at which the position component along the major axis is zero, and rescaling the three direction components of the ray so that the magnitude of the direction component along the major axis is one. The ray representative comprises: (i) the two position components of the translated position along the axes which are not the major axis, and (ii) the two rescaled direction components along the axes which are not the major axis.Type: GrantFiled: September 26, 2023Date of Patent: May 5, 2026Assignee: Imagination Technologies LimitedInventors: Peter Smith-Lacey, Simon Fenney
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Patent number: 12621457Abstract: Input pixel data having first, second and third channel data for each pixel of a block of data is received in raster scan order and is compressed in raster scan order using a block-based encoding scheme. The compressed pixel data is then output in raster scan order.Type: GrantFiled: December 1, 2021Date of Patent: May 5, 2026Assignee: Imagination Technologies LimitedInventors: Jeffery Thomas Bond, Gregory Alan Clark, Selina Hopton, Simon Fenney
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Patent number: 12603989Abstract: Image element values are determined from a compressed block of image data relating to a reference channel and non-reference channels. Compressed channel data is used to determine an initial data value relating to a channel. A decompressed data value is determined for the non-reference channels by: (i) reading an indication of a compression mode, the compression mode being either a channel decorrelating mode or a non-channel decorrelating mode, (ii) if the compression mode is non-channel decorrelating mode, determining the decompressed data value for the non-reference channel to be the determined initial data value relating to the non-reference channel for the image element value; (iii) if the compression mode is a channel decorrelating mode, determining the decompressed data value for the non-reference channel to be a function of the determined initial data value relating to the non-reference channel and the determined initial data value relating to one of the reference channels.Type: GrantFiled: December 7, 2023Date of Patent: April 14, 2026Assignee: Imagination Technologies LimitedInventors: Ilaria Martinelli, Simon Fenney, Kellie Marks, Paul Higginbottom
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Patent number: 12592720Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.Type: GrantFiled: December 26, 2023Date of Patent: March 31, 2026Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 12586250Abstract: A method and a compression unit are provided for compressing, into a block of compressed data, a block of sub-primitive presence indications for use in intersection testing in a rendering system. An ordered set of patches is obtained which represents the presence indications in the block of sub-primitive presence indications. At least two of the patches in the set of patches partially overlap with each other. Data defining the patches of the set of patches is stored in the block of compressed data. The data defining each of the patches defines a presence state of the patch and a position of the patch within the block of sub-primitive presence indications.Type: GrantFiled: May 30, 2023Date of Patent: March 24, 2026Assignee: Imagination Technologies LimitedInventors: Simon Fenney, Alper Ozkan
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Patent number: 12573094Abstract: A method and a decompression unit are provided for decompressing compressed data to determine a sub-primitive presence indication for use in intersection testing in a rendering system. A block of compressed data for a block of sub-primitive presence indications is received. An indication of a sample position within the block of sub-primitive presence indications for which a presence indication is to be determined is received. Data defining an ordered set of patches which represents the presence indications in the block of sub-primitive presence indications is read from the block of compressed data. The data defining each of the patches defines a presence state of the patch and a position of the patch within the block of sub-primitive presence indications. At least two of the patches in the set of patches partially overlap with each other. For one or more of the patches, it is determined whether the sample position is within that patch.Type: GrantFiled: May 30, 2023Date of Patent: March 10, 2026Assignee: Imagination Technologies LimitedInventors: Simon Fenney, Alper Ozkan
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Publication number: 20260065576Abstract: A method and an intersection testing module for performing intersection testing in a ray tracing system determines a first offset intersection distance which is equal to a sum of an intersection distance at which a ray intersects a first primitive and a first offset which is dependent upon the orientation of the first primitive. A second offset intersection distance is determined which is equal to a sum of an intersection distance at which the ray intersects a second primitive and a second offset which is dependent upon the orientation of the second primitive. The determined first and second offset intersection distances are compared to select the intersection of the ray with one of the first and second primitives.Type: ApplicationFiled: November 10, 2025Publication date: March 5, 2026Inventors: Peter Smith-Lacey, Simon Fenney, Gregory Clark, Rostam King
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Patent number: 12560816Abstract: A graphics processing system for a head mounted display (or other non-standard projection display) comprises a low latency distortion unit which is separate from a graphics processing unit in the graphics processing system. The low latency distortion unit receives pixel data generated by the graphics processing system using a standard projection and performs a mapping operation to introduce distortion which is dependent upon the optical properties of the optical arrangement within the head mounted display. The distorted pixel data which is generated by the low latency distortion unit is then output to the display in the head mounted display.Type: GrantFiled: August 29, 2023Date of Patent: February 24, 2026Assignee: Imagination Technologies LimitedInventor: Simon Fenney