Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230408822
    Abstract: A graphics processing system for a head mounted display (or other non-standard projection display) comprises a low latency distortion unit which is separate from a graphics processing unit in the graphics processing system. The low latency distortion unit receives pixel data generated by the graphics processing system using a standard projection and performs a mapping operation to introduce distortion which is dependent upon the optical properties of the optical arrangement within the head mounted display. The distorted pixel data which is generated by the low latency distortion unit is then output to the display in the head mounted display.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 21, 2023
    Inventor: Simon Fenney
  • Publication number: 20230401781
    Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y .
    Type: Application
    Filed: August 29, 2023
    Publication date: December 14, 2023
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Patent number: 11836368
    Abstract: A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Linling Zhang, Simon Fenney
  • Patent number: 11831342
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 28, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Linling Zhang
  • Patent number: 11830144
    Abstract: A graphics processing system includes a tiling unit configured to tile a first view of a scene into a plurality of tiles, a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view, and a rendering unit configured to render to a render target each of the identified tiles.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: November 28, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Michael Worcester, Stuart Smith
  • Patent number: 11830143
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: November 28, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11823317
    Abstract: A method of rendering geometry of a 3D scene for display on a non-standard projection display projects geometry of the 3D scene into a 2D projection plane, wherein image regions are defined in the projection plane, maps the geometry from the projection plane into an image space using transformations, wherein a respective transformation is defined for each image region, and renders the geometry in the image space to determine image values of an image to be displayed on the non-standard projection display. The transformations are configured for mapping the geometry into the image space so as to counteract distortion introduced by an optical arrangement of the non-standard projection display.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 21, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 11817885
    Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: November 14, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Linling Zhang
  • Patent number: 11816780
    Abstract: Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalised ray direction vector. Rather than normalising the ray direction vector, the intersection testing is performed on the unnormalised ray direction vector. This avoids the processing steps involved in normalising the ray direction vector.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 14, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Luke T. Peterson, Simon Fenney
  • Patent number: 11810240
    Abstract: A computer-implemented method of constructing a ray tracing acceleration structure for a scene defined with respect to an overall coordinate system. The acceleration structure includes a top-level acceleration structure (TLAS) having leaf nodes referencing one or more instances of a bottom-level acceleration structures (BLAS). The method comprises defining one or more TLAS nodes, for each TLAS node, determining a first bounding volume and associating the node with a transformation matrix that maps between the first bounding volume and a second bounding volume in the overall coordinate system.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 7, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20230351678
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 2, 2023
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Publication number: 20230343032
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 26, 2023
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Publication number: 20230334756
    Abstract: A method and an intersection testing module for performing intersection testing in a ray tracing system determines a first offset intersection distance which is equal to a sum of an intersection distance at which a ray intersects a first primitive and a first offset which is dependent upon the orientation of the first primitive. A second offset intersection distance is determined which is equal to a sum of an intersection distance at which the ray intersects a second primitive and a second offset which is dependent upon the orientation of the second primitive. The determined first and second offset intersection distances are compared to select the intersection of the ray with one of the first and second primitives.
    Type: Application
    Filed: February 27, 2023
    Publication date: October 19, 2023
    Inventors: Peter Smith-Lacey, Simon Fenney, Gregory Clark, Rostam King
  • Publication number: 20230334755
    Abstract: A method and an intersection testing module for performing intersection testing in a ray tracing system determines that a difference between an intersection distance at which a ray intersects a first primitive and an intersection distance at which the ray intersects a second primitive satisfies a comparison condition with respect to a threshold. It is determined that the orientations of the first and second primitives are different. The intersection of the ray with one of the first and second primitives is selected on the basis that the one of the first and second primitives has a particular orientation.
    Type: Application
    Filed: February 27, 2023
    Publication date: October 19, 2023
    Inventors: Peter Smith-Lacey, Simon Fenney, Gregory Clark, Rostam King
  • Publication number: 20230334757
    Abstract: A method and an intersection testing module for performing intersection testing in a ray tracing system determines if a difference between an intersection distance at which a ray intersects a first primitive and an intersection distance at which the ray intersects a second primitive satisfies a comparison condition with respect to a threshold, and if the orientations of the first and second primitives are different. If so the intersection of the ray with the one of the first and second primitives which has a particular orientation is selected.
    Type: Application
    Filed: February 27, 2023
    Publication date: October 19, 2023
    Inventors: Peter Smith-Lacey, Simon Fenney, Gregory Clark, Rostam King
  • Publication number: 20230326139
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 12, 2023
    Inventor: Simon Fenney
  • Publication number: 20230327682
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 12, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20230274503
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 31, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11741659
    Abstract: Determining whether a ray intersects a 3D axis-aligned box identifies the front-facing plane of the box which intersects the ray at a position furthest along a direction of the ray. Whether the ray intersects the box is determined by whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified. Whether the ray intersects the box is determined without performing a test to determine whether the ray intersects the identified front-facing plane at a position that is no further along the ray than a position at which the ray intersects the back-facing plane in the front-facing plane dimension.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Gregory Clark, Simon Fenney
  • Patent number: 11741655
    Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y . It is determined whether a third condition is satisfied, wherein the third condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x ? D y D z - C y ? D x D z ? "\[RightBracketingBar]" ? H y ? D x D z + H x ? D y D z .
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark