Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200313691
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Inventors: Simon Fenney, Linling Zhang
  • Publication number: 20200302690
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Publication number: 20200302691
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Application
    Filed: June 12, 2020
    Publication date: September 24, 2020
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 10783705
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 22, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20200287565
    Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventor: Simon Fenney
  • Patent number: 10768898
    Abstract: Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 8, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10769842
    Abstract: Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalised ray direction vector. Rather than normalising the ray direction vector, the intersection testing is performed on the unnormalised ray direction vector. This avoids the processing steps involved in normalising the ray direction vector.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 8, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Luke T. Peterson, Simon Fenney
  • Publication number: 20200272333
    Abstract: A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventors: Linling Zhang, Simon Fenney
  • Patent number: 10757415
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: August 25, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Patent number: 10740967
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: August 11, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Publication number: 20200250882
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Application
    Filed: April 15, 2020
    Publication date: August 6, 2020
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Patent number: 10726622
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 28, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10720940
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 21, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Linling Zhang
  • Patent number: 10719576
    Abstract: Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. mobile devices) which have limited processing resources. At each of a set of predetermined interpolation positions within an array of data points, a set of predetermined weights represent a bicubic interpolation which can be applied to the data points. For a plurality of the predetermined interpolation positions which surround the sampling position, the corresponding sets of predetermined weights and the data points are used to determine a plurality of surrounding interpolated values which represent results of performing the bicubic interpolation at the surrounding predetermined interpolation positions.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10707895
    Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 7, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10691360
    Abstract: A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression ratio and the compression ratio achieved by compressing just the first parts, none, one or more bits from the second parts, or from a data value derived from the second parts, may be appended to the compressed first parts. The method described may be lossy or may be lossless. A corresponding decompression method is also described.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 23, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Linling Zhang, Simon Fenney
  • Publication number: 20200177200
    Abstract: A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: Simon Fenney, Greg Clark, Alan Vines
  • Patent number: 10665009
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 26, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Publication number: 20200117426
    Abstract: Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 16, 2020
    Inventor: Simon Fenney
  • Patent number: 10600241
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney