Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200051332
    Abstract: A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles; a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view; and a rendering unit configured to render to a render target each of the identified tiles.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Simon Fenney, Michael Worcester, Stuart Smith
  • Patent number: 10528325
    Abstract: Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: January 7, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20200007150
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 2, 2020
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20200007866
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Application
    Filed: June 29, 2019
    Publication date: January 2, 2020
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Publication number: 20200007149
    Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 2, 2020
    Inventor: Simon Fenney
  • Publication number: 20200007152
    Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.
    Type: Application
    Filed: June 29, 2019
    Publication date: January 2, 2020
    Inventors: Simon Fenney, Linling Zhang
  • Publication number: 20200007151
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 2, 2020
    Inventors: Simon Fenney, Linling Zhang
  • Publication number: 20200007156
    Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 2, 2020
    Inventor: Simon Fenney
  • Publication number: 20190362550
    Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.
    Type: Application
    Filed: August 13, 2019
    Publication date: November 28, 2019
    Inventors: Piers Barber, Simon Fenney
  • Patent number: 10489974
    Abstract: A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles; a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view; and a rendering unit configured to render to a render target each of the identified tiles.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: November 26, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Michael Worcester, Stuart Smith
  • Publication number: 20190320209
    Abstract: A method of compressing image data comprising a set of image values each representing a position in image-value space so as to define an occupied region thereof. The method comprises selectively applying a series of compression transforms to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. The method further comprises identifying a set of one or more reference data items that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms from a fixed set of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the one or more reference data items. Each image data item in the set of image data items is encoded as a representation of the identified sequence of decompression transforms for that image data item.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 17, 2019
    Inventor: Simon Fenney
  • Publication number: 20190318532
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Application
    Filed: June 14, 2019
    Publication date: October 17, 2019
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Publication number: 20190311529
    Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 10, 2019
    Inventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
  • Publication number: 20190311537
    Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
    Type: Application
    Filed: June 7, 2019
    Publication date: October 10, 2019
    Inventors: Simon Fenney, Vasiliki Simaiaki
  • Publication number: 20190311536
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 10, 2019
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 10437726
    Abstract: Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10424114
    Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.
    Type: Grant
    Filed: January 19, 2019
    Date of Patent: September 24, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Piers Barber, Simon Fenney
  • Patent number: 10403004
    Abstract: Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of color decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10375418
    Abstract: There is a method of compressing image data comprising a set of image values each representing a position in image-value space so as to define an occupied region thereof. The method comprises selectively applying a series of compression transforms to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. The method further comprises identifying a set of one or more reference data items that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms from a fixed set of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the one or more reference data items. Each image data item in the set of image data items is encoded as a representation of the identified sequence of decompression transforms for that image data item.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 6, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20190236833
    Abstract: Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalised ray direction vector. Rather than normalising the ray direction vector, the intersection testing is performed on the unnormalised ray direction vector. This avoids the processing steps involved in normalising the ray direction vector.
    Type: Application
    Filed: April 4, 2019
    Publication date: August 1, 2019
    Inventors: Luke T. Peterson, Simon Fenney