Patents by Inventor Simon Fenney

Simon Fenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10977860
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 10972126
    Abstract: A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 6, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Greg Clark, Alan Vines
  • Publication number: 20210067172
    Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventor: Simon Fenney
  • Patent number: 10937228
    Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 2, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
  • Publication number: 20210049815
    Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 18, 2021
    Inventors: Piers Barber, Simon Fenney
  • Publication number: 20210042984
    Abstract: A method of rendering geometry of a 3D scene for display on a non-standard projection display projects geometry of the 3D scene into a 2D projection plane, wherein image regions are defined in the projection plane, maps the geometry from the projection plane into an image space using transformations, wherein a respective transformation is defined for each image region, and renders the geometry in the image space to determine image values of an image to be displayed on the non-standard projection display. The transformations are configured for mapping the geometry into the image space so as to counteract distortion introduced by an optical arrangement of the non-standard projection display.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Inventor: Simon Fenney
  • Publication number: 20210036713
    Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Inventors: Simon Fenney, Linling Zhang
  • Publication number: 20210019940
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Application
    Filed: October 2, 2020
    Publication date: January 21, 2021
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20210006261
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Application
    Filed: September 14, 2020
    Publication date: January 7, 2021
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 10878626
    Abstract: A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles; a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view; and a rendering unit configured to render to a render target each of the identified tiles.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 29, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Michael Worcester, Stuart Smith
  • Patent number: 10868565
    Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 15, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10861231
    Abstract: A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For each polygon, a determination is made whether that polygon is located at least partially inside a selected one of the smaller rectangular areas in the selected rectangular area. If so, which pixels of the plurality of pixels in the selected smaller rectangular area are inside the polygon are identified. Or, if that polygon is not located at least partially inside the selected smaller rectangular area, no further processing of the polygon is performed at one or more of the plurality of pixels in the smaller rectangular area.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 8, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Piers Barber, Simon Fenney
  • Patent number: 10853988
    Abstract: A method of rendering geometry of a 3D scene for display on a non-standard projection display projects geometry of the 3D scene into a 2D projection plane, wherein image regions are defined in the projection plane, maps the geometry from the projection plane into an image space using transformations, wherein a respective transformation is defined for each image region, and renders the geometry in the image space to determine image values of an image to be displayed on the non-standard projection display. The transformations are configured for mapping the geometry into the image space so as to counteract distortion introduced by an optical arrangement of the non-standard projection display.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: December 1, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Publication number: 20200357173
    Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 12, 2020
    Inventor: Simon Fenney
  • Patent number: 10832473
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 10, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20200351503
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Patent number: 10819367
    Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Linling Zhang
  • Patent number: 10810763
    Abstract: Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of colour decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: October 20, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10812101
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20200320161
    Abstract: Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. mobile devices) which have limited processing resources. At each of a set of predetermined interpolation positions within an array of data points, a set of predetermined weights represent a bicubic interpolation which can be applied to the data points. For a plurality of the predetermined interpolation positions which surround the sampling position, the corresponding sets of predetermined weights and the data points are used to determine a plurality of surrounding interpolated values which represent results of performing the bicubic interpolation at the surrounding predetermined interpolation positions.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventor: Simon Fenney