Patents by Inventor Simon Forey
Simon Forey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876649Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.Type: GrantFiled: January 20, 2022Date of Patent: January 16, 2024Assignee: Marvell Asia Pte LtdInventors: Luke Wang, Benjamin Smith, Basel Alnabulsi, Stephane Dallaire, Simon Forey, Karthik Raviprakash, Praveen Prabha, Benjamin T. Reyes
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Patent number: 11757355Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.Type: GrantFiled: December 1, 2021Date of Patent: September 12, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
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Publication number: 20230037860Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.Type: ApplicationFiled: January 20, 2022Publication date: February 9, 2023Inventors: Luke Wang, Benjamin Smith, Basel Alnabulsi, Stephane Dallaire, Simon Forey, Karthik Raviprakash, Praveen Prabha, Benjamin T. Reyes
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Publication number: 20200403503Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.Type: ApplicationFiled: September 8, 2020Publication date: December 24, 2020Inventors: Rajasekhar NAGULAPALLI, Simon FOREY, Parmanand MISHRA
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Patent number: 10804797Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.Type: GrantFiled: February 25, 2019Date of Patent: October 13, 2020Assignee: INPHI CORPORATIONInventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
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Patent number: 10771065Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.Type: GrantFiled: October 25, 2019Date of Patent: September 8, 2020Assignee: INPHI CORPORATIONInventors: Simon Forey, Parmanand Mishra, Michael S. Harwood, Rajasekhar Nagulapalli
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Patent number: 10763810Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.Type: GrantFiled: March 5, 2020Date of Patent: September 1, 2020Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Patent number: 10764092Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.Type: GrantFiled: November 12, 2019Date of Patent: September 1, 2020Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Publication number: 20200204131Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode Voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Inventors: Simon FOREY, Rajasekhar NAGULAPALLI, Parmanand MISHRA
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Patent number: 10622955Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.Type: GrantFiled: March 6, 2019Date of Patent: April 14, 2020Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Publication number: 20200084067Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Inventors: Simon FOREY, Rajasekhar NAGULAPALLI, Parmanand MISHRA
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Publication number: 20200059348Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Simon FOREY, Parmanand MISHRA, Michael S. HARWOOD, Rajasekhar NAGULAPALLI
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Patent number: 10505766Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.Type: GrantFiled: March 20, 2019Date of Patent: December 10, 2019Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Patent number: 10498526Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.Type: GrantFiled: February 8, 2019Date of Patent: December 3, 2019Assignee: INPHI CORPORATIONInventors: Simon Forey, Parmanand Mishra, Michael S. Harwood, Rajasekhar Nagulapalli
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Publication number: 20190207576Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.Type: ApplicationFiled: March 6, 2019Publication date: July 4, 2019Inventors: Simon FOREY, Rajasekhar NAGULAPALLI, Parmanand MISHRA
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Patent number: 10333527Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.Type: GrantFiled: October 8, 2018Date of Patent: June 25, 2019Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Patent number: 10284394Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.Type: GrantFiled: August 10, 2018Date of Patent: May 7, 2019Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Patent number: 10270409Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.Type: GrantFiled: May 16, 2017Date of Patent: April 23, 2019Assignee: INPHI CORPORATIONInventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
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Patent number: 10243570Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.Type: GrantFiled: July 28, 2017Date of Patent: March 26, 2019Assignee: INPHI CORPORATIONInventors: Simon Forey, Parmanand Mishra, Michael Harwood, Rajasekhar Nagulapalli
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Publication number: 20190044521Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.Type: ApplicationFiled: October 8, 2018Publication date: February 7, 2019Inventors: Simon FOREY, Rajasekhar NAGULAPALLI, Parmanand MISHRA