Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.

Abstract: There is provided a method and apparatus for performing an eye scan. Said apparatus comprises: a receiver for receiving input signals; an equaliser for processing said input signals; a data sampler for sampling said processed input signals at certain sampling points to produce a data output, said data sampler being controlled by a clock signal; an edge sampler for detecting the edges of the processed input signal; an early/late voter for deciding whether a current sampling point needs to be advanced or retarded. The early/late voter passes an Up/Down signal to an interpolator for maintaining said clock signal, said interpolator acting on said Up/Down signal to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.

Abstract: There is provided a Clock recovery apparatus comprising: an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein said early/late voter passes an Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and said interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.

Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.