Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.

Abstract: An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.

Abstract: A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

Abstract: A data processing apparatus has processing circuitry for executing first software at a first privilege level and second software at a second privilege level higher than the first privilege level. Attributes may be set by the first and second software to indicate whether execution of the data access instruction can be interrupted. For a predetermined type of data access instruction for which the second attribute set by the second software specifies that the instruction can be interrupted, the instruction may be set as interruptable even if the first attribute set by the first software specifies that the execution of the instruction cannot be interrupted.

Abstract: The present invention further relates to methods for treating a disease of iron metabolism and disease of fat or carbohydrate metabolism using a BMP agonist or antagonist

Abstract: Exception control circuitry controls exception handling for processing circuitry. In response to an initial exception occurring when the processing circuitry is in a given exception level, the initial exception to be handled in a target exception level, the exception control circuitry stores exception control information to at least one exception control register associated with the target exception level, indicating at least one property of the initial exception or of processor state at a time the initial exception occurred. When at least one exception intercept configuration parameter stored in a configuration register indicates that exception interception is enabled, after storing the exception control information, and before the processing circuitry starts processing an exception handler for handling the initial exception in the target exception level, the exception control circuitry triggers a further exception to be handled in a predetermined exception level.

Abstract: Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.

Abstract: Described are systems and methods for dynamically generating advertisements for presentation in an application executing on a client device, such as an application executing on a smart phone or tablet of a user. The described systems and methods select content items of specific content types based on determined user preference for content types as well as the device capabilities and access permissions of the application through which the advertisement is to be presented.

Abstract: A metal matrix composite comprises and/or consists of a uniform distribution of calcined ceramic particles having an average particle size of between 0.30 and 0.99 microns and a metal or alloy uniformly distributed with the ceramic particles and wherein the ceramic particles include oxides of two separate metals selected from the group consisting of Al, Li, Be, Pb, Fe, Ag, Au, Sn, Mg, Ti, Cu, and Zn, and in which said ceramic particles comprise at least 15 volume percent of the metal matrix sintered together and wherein said metal-matrix being machinable with a high speed steel (HSS) bit for greater than about one minute without excessive wear to the bit.

Abstract: A module for multiple network pluggable optics is disclosed. The module includes a faceplate, a plurality of cage assemblies, and a plurality of springs. The faceplate includes a front face, a first wall extending from the front face, the first wall including a heat exchanger, and a second wall extending from the front face, the second wall being offset from the first wall. The plurality of cage assemblies is positioned at least partially within a volume defined by the front face and the first and second walls. Each cage assembly is configured to receive a pluggable optical module. The plurality of springs are configured with one or more springs positioned between each cage assembly and the second wall to push the plurality of cage assemblies towards the first wall such that each pluggable optical module received into one of the plurality of cage assemblies is pressed against the heat exchanger.

Abstract: A platform includes a housing with a front side, a rear side opposite the front side, a right side adjacent to both the front side and the rear side, and a left side opposite the right side and adjacent to both the front side and the rear side, wherein airflow in the platform is between the front side and the rear side or between the front side and the front side; one or more modules in the housing each including a plurality of cages supporting removable interface cards, wherein the airflow includes an air path that is over the one or more modules between a bottom portion of the one or more modules and a top portion of the one or more modules; and at least one dust cap in one of the plurality of cages, wherein the dust cap includes an air filter medium enabling airflow at an intermediate point of the air path.

Abstract: An apparatus has first processing circuitry and second processing circuity. The second processing circuitry has at least one hardware mechanism providing a greater level of fault protection or fault detection than is provided for the first processing circuitry. Coherency control circuitry controls access to data from at least part of a shared address space by the first and second processing circuitry according to an asymmetric coherency protocol in which a local-only update of data in a local cache of the first processing circuitry is restricted in comparison to a local-only update of data in a local cache of the second processing circuitry.

Abstract: A method, or corresponding dynamic display system, for customizing a controller of a display system includes presenting a visual stimulus to a subject at at least one known location relative to the subject's eye gaze; measuring brain activity of the subject's left and right brain hemispheres in response to the subject's viewing of the stimulus; processing the measured brain activity to determine a frequency-dependent metric of the measured brain activity; assessing independent cognitive capacities of the subject's left and right brain hemispheres based on the frequency-dependent metric; and adjusting a function of the controller in the display system according to the assessed independent capacities, such as by adjusting the function to change a stimulus load in a visual hemifield according to the brain activity in the contralateral brain hemisphere. Example applications include head-up display (HUD), augmented reality (AR) or virtual reality (VR) display systems, and brain injury assessment systems.

Abstract: An apparatus and method are provided for performing data processing operations. The apparatus has processing circuitry for performing data processing operations configured to operate in a normal mode and a memory region management mode. A memory is used to store data accessed by the processing circuitry when performing the data processing operations. A memory region table is provided to define accessibility control information for each of a number of memory regions within the memory. An access control mechanism controls access to the memory in response to an access request issued by the processing circuitry, and a memory protection unit providing a bypass indication for one or more memory regions is referenced by the access control mechanism when the processing circuitry is in the memory region management mode.

Abstract: The execution of time intensive instructions can lead to critical events being responded to late or not being responded to at all. An information processing apparatus comprises processing circuitry (60) for executing instructions comprising one or more time intensive instructions and exception generating circuitry (100) for generating at least one exception for the processing circuitry. The processing circuitry maintains a control value (20) for indicating whether or not the time intensive instructions can be executed. When a time intensive instruction is encountered, if the control value indicates that time intensive instructions cannot be executed then a first exception triggers the processing circuitry to suppress execution of the time intensive instruction. Alternatively, if the control value indicates that time intensive instructions can be executed, then the time intensive instruction is executed.

Abstract: An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction.

Abstract: Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided.

Abstract: A receptacle runner assembly including a pair of opposed sub-assemblies configured to be arranged in a spaced relationship at opposed sides of the receptacle, each sub-assembly including a runner configured to be carried along a first track to be movable in a first direction, a first linkage being pivotally connectable to each of the receptacle and the runner, a bearing securable relative to the receptacle, and a bearing surface configured to be arranged, in use, to extend transverse to the first direction to allow carrying the bearing, wherein the bearings and bearing surfaces are configured to cooperate to displace the receptacle in a direction perpendicular to the first direction while the runners are moving in the first direction.

Abstract: A computer-implemented method for supplementing measurement results of automated analyzers is presented. The method includes obtaining, at a computer device, a result of a measurement performed by an automated analyzer, the computer device and the automated analyzer being located within a privileged computer network, obtaining a context related algorithm associated with the result of the measurement defining one or more triggering conditions and context related information from a computer device residing outside of the privileged computer network at the computer device and processing the result of the measurement by using the context related algorithm to generate a context specific supplement to the result of the measurement at the computer device.