Patents by Inventor Simon Steely

Simon Steely has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8769201
    Abstract: A technique to enable resource allocation optimization within a computer system. In one embodiment, a gradient partition algorithm (GPA) module is used to continually measure performance and adjust allocation to shared resources among a plurality of data classes in order to achieve optimal performance.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: William Hasenplaugh, Joel Emer, Tryggve Fossum, Aamer Jaleel, Simon Steely
  • Publication number: 20100138609
    Abstract: A technique to enable resource allocation optimization within a computer system. In one embodiment, a gradient partition algorithm (GPA) module is used to continually measure performance and adjust allocation to shared resources among a plurality of data classes in order to achieve optimal performance.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Inventors: William Hasenplaugh, Joel Emer, Tryggve Fossum, Aamer Jaleel, Simon Steely
  • Publication number: 20060230233
    Abstract: A technique to share cache lines among a plurality of bus agents. Embodiments of the invention comprise at least one technique to allow a number of agents, such as a processor or software program being executed by a processor, within a computer system or computer network to transfer ownership of a locked (“owned”) cache line, under certain circumstances, without incurring as much of the operational overhead and resulting performance degradation of many prior art techniques.
    Type: Application
    Filed: April 11, 2005
    Publication date: October 12, 2006
    Inventors: Simon Steely, Stephen Doren
  • Publication number: 20060143400
    Abstract: An embodiment of the present invention is a technique to perform replacement in a non-uniform access cache structure. A cache memory stores data and associated tags in a non-uniform access manner. The cache memory has a plurality of memory banks arranged according to a distance hierarchy with respect to one of a processor and a processor core. The distance hierarchy includes a lowest latency bank and a highest latency bank. A controller performs a non-uniform pseudo least recently used (LRU) replacement on the cache memory.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 29, 2006
    Inventor: Simon Steely
  • Publication number: 20060041724
    Abstract: A technique to share cache lines among a plurality of bus agents. Embodiments of the invention comprise at least one technique to allow a number of agents, such as a processor or software program being executed by a processor, within a computer system or computer network to access a locked (“owned”) cache line, under certain circumstances, without incurring as much of the operational overhead and resulting performance degradation of many prior art techniques.
    Type: Application
    Filed: August 17, 2004
    Publication date: February 23, 2006
    Inventors: Simon Steely, Stephen Van Doren
  • Publication number: 20050240731
    Abstract: Methods for storing replacement data in a multi-way associative cache are disclosed. One method comprises logically dividing the cache's cache sets into segments of at least one cache way; searching a cache set in accordance with a segment search sequence for a segment currently comprising a way which has not yet been accessed during a current cycle of the segment search sequence; searching the current segment in accordance with a way search sequence for a way which has not yet been accessed during a current way search cycle; and storing the replacement data in a first way which has not yet been accessed during a current cycle of the way search sequence. A cache controller that performs such methods is also disclosed.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 27, 2005
    Inventor: Simon Steely
  • Publication number: 20050198440
    Abstract: A system includes a first node that broadcasts a request for data. A second node having a first state associated with the data defines the second node as an ordering point for the data. The second node provides a response to the first node that transfers the ordering point to the first node in response to the request for the data.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 8, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050198187
    Abstract: A multi-processor system includes a requesting node that provides a first request for data to a home node. The requesting node being operative to provide a second request for the data to at least one predicted node in parallel with first request. The requesting node receives at least one coherent copy of the data from at least one of the home node and the at least one predicted node.
    Type: Application
    Filed: January 15, 2004
    Publication date: September 8, 2005
    Inventors: Gregory Tierney, Simon Steely
  • Publication number: 20050198192
    Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 8, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160233
    Abstract: A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160230
    Abstract: Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Doren, Gregory Tiemey, Simon Steely
  • Publication number: 20050160430
    Abstract: Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of owner predictors in response to a change in an ownership state of the block of data. The update message comprises an address tag associated with the block of data and an identification associated with an owner node of the block of data.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Simon Steely, Gregory Tierney
  • Publication number: 20050160231
    Abstract: A system comprises a first node having an associated cache including data having an associated first cache state. The first cache state is capable of identifying the first node as being an ordering point for serializing requests from other nodes for the data.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160209
    Abstract: A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160132
    Abstract: One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Simon Steely, Gregory Tierney
  • Publication number: 20050160232
    Abstract: Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Gregory Tierney, Stephen Van Doren, Simon Steely
  • Publication number: 20050160237
    Abstract: A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Gregory Tierney, Stephen Van Doren, Simon Steely
  • Publication number: 20050160236
    Abstract: A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Gregory Tierney, Stephen Van Doren, Simon Steely
  • Publication number: 20050160238
    Abstract: A system comprises a first node that provides a source broadcast request for data. The first node is operable to respond in a first manner to other source broadcast requests for the data while the source broadcast for the data is pending at the first node. The first node is operable to respond in a second manner to the other source broadcast requests for the data in response to receiving an ownership data response at the first node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Simon Steely, Gregory Tierney, Stephen Van Doren
  • Publication number: 20050160240
    Abstract: Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely