Patents by Inventor Simon Steely

Simon Steely has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050198440
    Abstract: A system includes a first node that broadcasts a request for data. A second node having a first state associated with the data defines the second node as an ordering point for the data. The second node provides a response to the first node that transfers the ordering point to the first node in response to the request for the data.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 8, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050198192
    Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 8, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160240
    Abstract: Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160233
    Abstract: A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160236
    Abstract: A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Gregory Tierney, Stephen Van Doren, Simon Steely
  • Publication number: 20050160238
    Abstract: A system comprises a first node that provides a source broadcast request for data. The first node is operable to respond in a first manner to other source broadcast requests for the data while the source broadcast for the data is pending at the first node. The first node is operable to respond in a second manner to the other source broadcast requests for the data in response to receiving an ownership data response at the first node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Simon Steely, Gregory Tierney, Stephen Van Doren
  • Publication number: 20050160209
    Abstract: A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160430
    Abstract: Systems and methods are disclosed for updating owner predictor structures. In one embodiment, a multi-processor system includes an owner predictor control that provides an ownership update message corresponding to a block of data to at least one of a plurality of owner predictors in response to a change in an ownership state of the block of data. The update message comprises an address tag associated with the block of data and an identification associated with an owner node of the block of data.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Simon Steely, Gregory Tierney
  • Publication number: 20050160232
    Abstract: Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Gregory Tierney, Stephen Van Doren, Simon Steely
  • Publication number: 20050160230
    Abstract: Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Doren, Gregory Tiemey, Simon Steely
  • Publication number: 20050160231
    Abstract: A system comprises a first node having an associated cache including data having an associated first cache state. The first cache state is capable of identifying the first node as being an ordering point for serializing requests from other nodes for the data.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Doren, Gregory Tierney, Simon Steely
  • Publication number: 20050160237
    Abstract: A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Gregory Tierney, Stephen Van Doren, Simon Steely
  • Publication number: 20050160132
    Abstract: One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Stephen Van Doren, Simon Steely, Gregory Tierney
  • Publication number: 20050160235
    Abstract: A system comprises a first node including data having an associated state. The associated state of the data at the first node is a modified state. The system also comprises a second node operative to provide a non-migratory source broadcast request for the data. The first node is operative in response to the non-migratory source broadcast request to provide the data to the second node and to transition the associated state of the data at the first node from the modified state to an owner state without updating memory. The second node is operative to receive the data from the first node and assign a shared state to an associated state of the data at the second node.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventors: Simon Steely, Stephen Van Doren, Gregory Tierney
  • Publication number: 20050154805
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requests. The multi-processor system may comprise a first cache that retains cache data associated with program instructions employing data from speculative data fills, and a second cache that retains cache data associated with data from speculative data fills that have been determined to be coherent.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 14, 2005
    Inventors: Simon Steely, Gregory Tierney
  • Publication number: 20050154863
    Abstract: Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a speculative data fill to a source processor in response to the speculative source request. The processor system provides a coherent data fill to the processor in response to the system source request.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 14, 2005
    Inventors: Simon Steely, Gregory Tierney, Stephen Van Doren
  • Publication number: 20050154832
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 14, 2005
    Inventors: Simon Steely, Gregory Tierney
  • Publication number: 20050154834
    Abstract: One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request. The multi-processor system can further comprise a non-retired store cache that retains non-retired store data based on program instructions to store data into a data cache associated with the processor. The non-retired store data can be written to the data cache if data of a speculative fill associated with the non-retired store data is determined to be coherent. Other apparatus and methodologies are disclosed.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 14, 2005
    Inventors: Simon Steely, Gregory Tierney
  • Publication number: 20050154836
    Abstract: Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 14, 2005
    Inventors: Simon Steely, Gregory Tierney
  • Publication number: 20050154865
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 14, 2005
    Inventors: Simon Steely, Gregory Tierney