Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.

Abstract: Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in response to a cache miss at a local cache. A shared cache structure may provide at least one speculative data fill and a coherent data fill of the desired data to at least one of the plurality of processor cores in response to a request from the at least one processor core. A processor scoreboard arbitrates the requests for the desired data. A speculative data fill of the desired data is provided to the at least one processor core. The coherent data fill of the desired data may be provided to the at least one processor core in a determined order.

Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are provided in response to source requests. The multi-processor system may comprise a first register file that retains register values associated with program instruction employing data from speculative fills, and a second register file that retains register values associated with data from speculative fills that have been determined to be coherent.

Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.

Abstract: A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction value, including a sequential prediction hint and a branch prediction hint, is associated with each instruction stored in the I-cache. The prediction value may either be stored with the I-cache data, or in a separate memory included before the I-cache. If the predicted value is incorrect, the predicted hint is `trained` to provide a higher degree of accuracy for repetitive instruction stream operation. Processor performance is additionally improved by providing a branch hint that allows for smoother transition between changing instruction streams.

Abstract: A high-speed data transfer unit that transfers data between a central processing unit in a data processing system and an external device such as a disk drive. The transfer unit has two control units, one that controls transfers with the central processing unit under control of port control commands from the processor, and the other that controls transfers with the external device under control of operational commands.