Patents by Inventor Simone Rascuna

Simone Rascuna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150372093
    Abstract: A switching device, such as a barrier junction Schottky diode, has a body of silicon carbide of a first conductivity type housing switching regions of a second conductivity type. The switching regions extend from a top surface of the body and delimit body surface portions between them. A contact metal layer having homogeneous chemical-physical characteristics extends on and in direct contact with the top surface of the body and forms Schottky contact metal portions with the surface portions of the body and ohmic contact metal portions with the switching regions. The contact metal layer is formed by depositing a nickel or cobalt layer on the body and carrying out a thermal treatment so that the metal reacts with the semiconductor material of the body and forms a silicide.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 24, 2015
    Inventors: Mario Giuseppe Saggio, Simone Rascuna, Fabrizio Roccaforte
  • Patent number: 8901652
    Abstract: An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: December 2, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera, Simone Rascuna′
  • Patent number: 8012832
    Abstract: A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by a second implant step with a second implant dose, and forming a surface semiconductor layer. The process also includes forming body regions of the second type of conductivity aligned with the first sub-regions, and carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region aligned and in electric contact with the body regions.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina, Simone Rascuna
  • Publication number: 20110049616
    Abstract: An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 3, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe SAGGIO, Alfio GUARNERA, Simone RASCUNA'
  • Publication number: 20110034010
    Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
    Type: Application
    Filed: October 15, 2010
    Publication date: February 10, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina, Simone Rascuna
  • Patent number: 7838927
    Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: November 23, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina, Simone Rascuna
  • Publication number: 20090001460
    Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
    Type: Application
    Filed: January 8, 2008
    Publication date: January 1, 2009
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina, Simone Rascuna
  • Publication number: 20080224204
    Abstract: A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by means of a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by means of a second implant step with a second implant dose, forming a surface semiconductor layer wherein body regions of the second type of conductivity are formed being aligned with the first sub-regions, carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region being aligned and in electric contact with the body regions.
    Type: Application
    Filed: January 8, 2008
    Publication date: September 18, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina, Simone Rascuna