Patents by Inventor Soichi Inoue
Soichi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230251582Abstract: A measurement apparatus which measures a relative positional displacement amount of a partial pattern to another pattern in a complex pattern on a surface of an object, includes: a measurement part to measure two-dimensional intensity distributions having a first and a second two-dimensional intensity distribution, the first distribution being formed by applying first light having a first shape to a region on which the complex pattern is measured and detecting only zero order diffraction light from the region via a first filter, and the second distribution being formed by applying second light having a second shape to the region and detecting only zero order diffraction light from the region via a second filter; a storage part to store measurement data indicating the distributions; and a calculation part to form a synthesized intensity distribution obtained by the two-dimensional intensity distributions to calculate a positional displacement amount of the partial pattern.Type: ApplicationFiled: September 9, 2022Publication date: August 10, 2023Applicant: Kioxia CorporationInventors: Kentaro KASA, Soichi INOUE, Satoshi TANAKA, Hiroyuki TANIZAKI
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Patent number: 10811252Abstract: A pattern-forming method includes forming a first film above a material to be processed, processing the first film into a pattern to be formed in the material to be processed, providing a second film on the first film and the material to be processed, supplying a precursor containing at least one of a metal material or a semiconductor material to the second film, removing the first film, and processing the material to be processed using the second film impregnated with at least one of the metal material and the semiconductor material, as a mask.Type: GrantFiled: August 30, 2018Date of Patent: October 20, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ryosuke Yamamoto, Ryuichi Saito, Seiji Morita, Ryoichi Suzuki, Takeharu Motokawa, Shinichi Ito, Soichi Inoue
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Publication number: 20190259606Abstract: A pattern-forming method includes forming a first film above a material to be processed, processing the first film into a pattern to be formed in the material to be processed, providing a second film on the first film and the material to be processed, supplying a precursor containing at least one of a metal material or a semiconductor material to the second film, removing the first film, and processing the material to be processed using the second film impregnated with at least one of the metal material and the semiconductor material, as a mask.Type: ApplicationFiled: August 30, 2018Publication date: August 22, 2019Inventors: Ryosuke YAMAMOTO, Ryuichi SAITO, Seiji MORITA, Ryoichi SUZUKI, Takeharu MOTOKAWA, Shinichi ITO, Soichi INOUE
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Patent number: 9922991Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.Type: GrantFiled: September 16, 2016Date of Patent: March 20, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya Kamigaki, Isahiro Hasegawa, Shinichi Ito, Soichi Inoue, Tatsuhiko Higashiki, Kei Hattori, Koichi Matsuno, Seiji Morita
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Publication number: 20170271363Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.Type: ApplicationFiled: September 16, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tetsuya Kamigaki, Isahiro Hasegawa, Shinichi Ito, Soichi Inoue, Tatsuhiko Higashiki, Kei Hattori, Koichi Matsuno, Seiji Morita
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Patent number: 8885949Abstract: According to the pattern shape determining method of the embodiment, a first reference position of a pattern shape is set on a first pattern and a second reference position of a pattern shape is set on a second pattern. Moreover, an allowable dimensional difference between the first pattern and the second pattern is set to a value corresponding to a distance from the first reference position. Then, it is determined whether the second pattern has a pattern shape identical with the first pattern, based on whether a dimensional difference between the first pattern and the second pattern is within a range of an allowable dimensional difference set at a position at which the dimensional difference is calculated.Type: GrantFiled: September 21, 2011Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigeki Nojima, Tetsuaki Matsunawa, Soichi Inoue
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Patent number: 8654313Abstract: According to one embodiment, on a substrate, a resist layer is laminated on an upper side of a pattern formation layer on which a desired pattern is formed. A diffraction pattern that diffracts exposure light irradiated on the substrate is formed further on the upper side than the resist layer. Overall exposure is performed from above the diffraction pattern using a deformed light having illumination light source shape determined according to the desired pattern. Diffracted light diffracted on the diffraction pattern by the exposure is irradiated on the resist layer.Type: GrantFiled: November 23, 2010Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Takahashi, Takashi Sato, Satoshi Tanaka, Soichi Inoue, Takamasa Takaki
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Patent number: 8440376Abstract: According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.Type: GrantFiled: January 14, 2011Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Kazuya Fukuhara, Michiya Takimoto, Hidefumi Mukai, Soichi Inoue
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Patent number: 8261214Abstract: A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.Type: GrantFiled: December 3, 2009Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Shimon Maeda, Masahiro Miyairi, Soichi Inoue
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Patent number: 8183119Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.Type: GrantFiled: March 15, 2010Date of Patent: May 22, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
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Patent number: 8163611Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.Type: GrantFiled: December 22, 2006Date of Patent: April 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
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Patent number: 8158527Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.Type: GrantFiled: March 15, 2010Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
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Publication number: 20120076424Abstract: According to the pattern shape determining method of the embodiment, a first reference position of a pattern shape is set on a first pattern and a second reference position of a pattern shape is set on a second pattern. Moreover, an allowable dimensional difference between the first pattern and the second pattern is set to a value corresponding to a distance from the first reference position. Then, it is determined whether the second pattern has a pattern shape identical with the first pattern, based on whether a dimensional difference between the first pattern and the second pattern is within a range of an allowable dimensional difference set at a position at which the dimensional difference is calculated.Type: ApplicationFiled: September 21, 2011Publication date: March 29, 2012Inventors: Shigeki NOJIMA, Tetsuaki Matsunawa, Soichi Inoue
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Patent number: 8142961Abstract: A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.Type: GrantFiled: March 4, 2010Date of Patent: March 27, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Satoshi Tanaka, Shigeki Nojima, Koji Hashimoto, Soichi Inoue
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Patent number: 8121387Abstract: A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information.Type: GrantFiled: March 20, 2008Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuyo Asano, Shinji Yamaguchi, Satoshi Tanaka, Soichi Inoue, Masamitsu Itoh, Osamu Ikenaga
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Patent number: 8086973Abstract: A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.Type: GrantFiled: December 18, 2007Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Yoshida, Soichi Inoue
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Patent number: 8046722Abstract: A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.Type: GrantFiled: February 11, 2009Date of Patent: October 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
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Publication number: 20110177458Abstract: According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.Type: ApplicationFiled: January 14, 2011Publication date: July 21, 2011Inventors: Toshiya KOTANI, Kazuya Fukuhara, Michiya Takimoto, Hidefumi Mukai, Soichi Inoue
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Patent number: 7966584Abstract: Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.Type: GrantFiled: April 8, 2009Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Suigen Kyoh, Toshiya Kotani, Soichi Inoue
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Patent number: RE43659Abstract: A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.Type: GrantFiled: November 12, 2010Date of Patent: September 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue