Patents by Inventor Soichi Inoue

Soichi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090233189
    Abstract: A method of obtaining exposure correction information includes adjusting intensity of light incident on a photomask so that intensity of light output from the photomask has a desired distribution, and includes obtaining the exposure correction information as a distribution of the adjusted intensity of light incident on the photomask.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Inventors: Kazuya FUKUHARA, Satoshi TANAKA, Masamitsu ITOH, Soichi INOUE
  • Publication number: 20090199148
    Abstract: Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.
    Type: Application
    Filed: April 8, 2009
    Publication date: August 6, 2009
    Inventors: Suigen Kyoh, Toshiya Kotani, Soichi Inoue
  • Publication number: 20090186429
    Abstract: A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
    Type: Application
    Filed: February 11, 2009
    Publication date: July 23, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7556896
    Abstract: An inspection method, includes obtaining a first optical characteristic of a projection optical system by transferring an image of an aberration measurement unit of a photomask on a first resist film coated on a first wafer by use of a first polarized exposure light; obtaining a second optical characteristic of the projection optical system by transferring the image of the aberration measurement unit on a second resist film coated on a second wafer by use of a second exposure light having a polarization state different from the first exposure light; and calculating a difference between the first and second optical characteristics.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7541136
    Abstract: Disclosed is a mask comprising a first area including a first surrounding area in which a halftone phase shift film or a stacked film of a halftone phase shift film and an opaque film is provided on a transparent substrate, and a first opening area surrounded by the first surrounding area, and a second area including a second surrounding area in which a halftone phase shift film is provided on the transparent substrate and a second opening area surrounded by the second surrounding area, wherein a transparent film is provided in at least a part of the second opening area, the transparent film being configured to give a predetermined phase difference to exposure light passing through that part of the second opening area in which the transparent film is provided relative to exposure light passing through the second surrounding area.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: June 2, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoko Izuha, Hideki Kanai, Soichi Inoue, Shingo Kanamitsu, Shinichi Ito
  • Patent number: 7526748
    Abstract: A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: April 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Shigeki Nojima, Soichi Inoue
  • Patent number: 7523437
    Abstract: Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: April 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Suigen Kyoh, Toshiya Kotani, Soichi Inoue
  • Patent number: 7506301
    Abstract: A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: March 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7499582
    Abstract: There is disclosed a method for inspecting a defect in a photomask which is produced by using a graphic data, that matches mask data or is produced by subjecting mask data to correction of a process conversion difference relating to at least a line width. The method includes the following steps. Inspection data is produced by correcting a pattern of mask data so as to substantially match a planar shape of a pattern of a photomask to be produced by using the graphic data. A pattern of a produced photomask is compared with a pattern of the inspection data. Portions where planar shapes of the pattern of the inspection data and the pattern of the produced photomask do not match are extracted. A defect is distinguished from the portions where the planer shapes do not match.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Suigen Kyoh, Shinji Yamaguchi, Soichi Inoue
  • Publication number: 20090031262
    Abstract: A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the design layout, calculating a first evaluation value for a finished planar shape of a resist pattern corresponding to the design layout based on the first OPC, determining whether the first evaluation value satisfies a predetermined value, if the first evaluation value does not satisfy the predetermined value, locally altering the design layout, performing second OPC on the altered design layout, calculating a second evaluation value for the altered design layout, performing second determination, and if the second evaluation value satisfies the predetermined value, outputting the result of OPC and the first and second evaluation values.
    Type: Application
    Filed: July 25, 2008
    Publication date: January 29, 2009
    Inventors: Shimon Maeda, Suigen Kyoh, Soichi Inoue
  • Patent number: 7482661
    Abstract: A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Publication number: 20090021711
    Abstract: A method of inspecting an exposure system uses a mask pattern including a first and a second mask pattern, the first pattern being formed in a line-and-space of a first pitch, the second pattern being disposed in parallel with the first mask pattern and formed in a line-and-space of a second pitch. The method includes illuminating the mask pattern with inspection light at a first angle with the optical axis of the illumination light from a light source, allowing the first mask pattern to diffract the inspection light to generate first diffraction light, and allowing the second mask pattern to diffract the inspection light to generate second diffraction light. The first angle is to allow the first diffraction light to be diffracted asymmetrically with the optical axis into the projection optical system and the second diffraction light to be diffracted symmetrically with the optical axis into the projection optical system.
    Type: Application
    Filed: July 16, 2008
    Publication date: January 22, 2009
    Inventors: Takashi Sato, Soichi Inoue
  • Publication number: 20090011370
    Abstract: A pattern forming method using two layers of resist pattern stacked one on the other has been disclosed. First, a first resist pattern is formed on a to-be-processed film. The first resist pattern is slimmed. On the slimmed first resist pattern and to-be-processed film, a second resist pattern is formed. With the first and second resist patterns as a mask, the film is processed.
    Type: Application
    Filed: June 10, 2008
    Publication date: January 8, 2009
    Inventors: Hiroko Nakamura, Koji Hashimoto, Soichi Inoue, Toshiya Kotani
  • Patent number: 7473495
    Abstract: A method of creating a predictive model of a process proximity effect comprises: preparing a predictive model of a process proximity effect including a non-determined parameter; and determining the non-determined parameter, the method comprises: preparing a pattern group for modeling, the pattern group comprising a plurality of repetition patterns, the plurality of repetition patterns being obtained by changing a first and second dimensions of a repetition pattern which repeats a basic pattern, the first dimension defining the basic pattern, and the second dimension defining repetition of the basic pattern; selecting a predetermined repetition pattern from the pattern group for modeling, the basic pattern of the predetermined repetition pattern corresponding to a pattern which is to be formed on a wafer and has a predetermined dimension; and determining the non-determined parameter in the predictive model based on the predetermined repetition pattern and the pattern having the predetermined dimension.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 6, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tanaka, Soichi Inoue, Koji Hashimoto, Shigeru Hasebe
  • Patent number: 7474386
    Abstract: There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: January 6, 2009
    Assignees: Kabushiki Kaisha Toshiba, Shin-Etsu Handotai Co., Ltd., Nikon Corporation
    Inventors: Tadahito Fujisawa, Soichi Inoue, Makoto Kobayashi, Masashi Ichikawa, Tsuneyuki Hagiwara, Kenichi Kodama
  • Publication number: 20080250381
    Abstract: A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturi
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Inventors: Toshiya KOTANI, Yasunobu Kai, Soichi Inoue, Satoshi Tanaka, Shigeki Nojima, Kazuyuki Masukawa, Koji Hashimoto
  • Publication number: 20080232671
    Abstract: A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 25, 2008
    Inventors: Mitsuyo ASANO, Shinji Yamaguchi, Satoshi Tanaka, Soichi Inoue, Masamitsu Itoh, Osamu Ikenaga
  • Publication number: 20080216046
    Abstract: A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.
    Type: Application
    Filed: December 18, 2007
    Publication date: September 4, 2008
    Inventors: Kenji YOSHIDA, Soichi Inoue
  • Patent number: 7396621
    Abstract: A method of manufacturing a semiconductor device includes preparing a projection exposure apparatus and a photomask, the photomask having a transparent substrate and a light shield film arranged in patterns to be transferred to a resist film on a wafer. The patterns include a circuit mask pattern, and first and second mark mask patterns having dimensions which change in accordance with exposure of the resist film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahito Fujisawa, Soichi Inoue, Satoshi Tanaka, Masafumi Asano
  • Patent number: 7371483
    Abstract: Disclosed is a method for manufacturing a mask for focus monitoring, comprising forming a first opening portion and a second opening portion in a surface region of a transparent substrate, the second opening portion having a pattern shape corresponding to a pattern shape of the first opening portion, and being surrounded by a stack film formed of a halftone film on the transparent substrate and an opaque film on the halftone film, and radiating a charged beam onto a first region which includes an edge of the second opening portion and inside and outside regions which are respectively located inward and outward of the edge of the second opening portion, to etch that part of the transparent substrate which corresponds to the inside region.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shingo Kanamitsu, Takashi Hirano, Kyoko Izuha, Soichi Inoue, Shinichi Ito