Patents by Inventor Soichi Inoue

Soichi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7365830
    Abstract: There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: April 29, 2008
    Assignees: Kabushiki Kaisha Toshiba, Shin-Etsu Handotai Co., Ltd., Nikon Corporation
    Inventors: Tadahito Fujisawa, Soichi Inoue, Makoto Kobayashi, Masashi Ichikawa, Tsuneyuki Hagiwara, Kenichi Kodama
  • Patent number: 7353145
    Abstract: A computer implemented method for correcting a mask pattern, includes: preparing a designed mask pattern; obtaining a rough corrected mask pattern from the designed mask pattern by applying a rough correction; and obtaining a precision corrected mask pattern from the rough corrected mask pattern by applying a precision correction using a model based correction method with a precision model that simulates a transferred image of an exposure apparatus.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tanaka, Soichi Inoue
  • Publication number: 20080072208
    Abstract: A mask defect inspecting method comprises preparing detection sensitivities of defects on a plurality of portions of a mask pattern on a photomask, the detection sensitivities being determined according to influences of the defects upon a wafer, and inspecting defects on the plurality of portions based on the detection sensitivities.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 20, 2008
    Inventors: Shinji Yamaguchi, Soichi Inoue, Satoshi Tanaka, Mari Inoue
  • Patent number: 7327449
    Abstract: An inspection method for an exposure apparatus for illuminating a photomask on a first installation member by an illumination optical system, and for projecting an image of a pattern of the photomask onto a substrate on a second installation member through a projection optical system, the inspection method comprises disposing an inspection photosensitive substrate as the substrate on the second installation member, illuminating a first region which doesn't include a pupil end of the projection optical system and a second region which includes the pupil end of the projection optical system and which isn't overlapped with the first region, in a state in which a surface of the photosensitive substrate and a surface of a secondary light source of the illumination optical system are optically conjugate with each other, and inspecting an illumination axis offset of the exposure apparatus based on a pattern obtained by developing the photosensitive substrate.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: February 5, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Soichi Inoue
  • Patent number: 7295304
    Abstract: A mask defect inspecting method comprises preparing detection sensitivities of defects on a plurality of portions of a mask pattern on a photomask, the detection sensitivities being determined according to influences of the defects upon a wafer, and inspecting defects on the plurality of portions based on the detection sensitivities.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: November 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Yamaguchi, Soichi Inoue, Satoshi Tanaka, Mari Inoue
  • Publication number: 20070259280
    Abstract: A photomask transferring a light shield film pattern formed on a transparent substrate by a projection exposure apparatus, comprising a circuit pattern for transferring a predetermined pattern to a resist film, and an exposure monitor mark, the exposure monitor mark being formed in a manner that blocks having a predetermined width p, which are not resolved by the projection exposure apparatus, are intermittently or continuously arrayed along one direction, light shield and transmission portions are arrayed along one direction in each of the blocks, the blocks are arrayed so that a dimension ratio of the light shield and transmission portions of the blocks simply changes and the phase difference of exposure light passing through adjacent light transmission portions is approximately 180°.
    Type: Application
    Filed: June 27, 2007
    Publication date: November 8, 2007
    Inventors: Tadahito Fujisawa, Soichi Inoue, Satoshi Tanaka, Masafumi Asano
  • Patent number: 7286216
    Abstract: An inspection method for an exposure apparatus for illuminating a photomask on a first installation member by an illumination optical system, and for projecting an image of a pattern of the photomask onto a substrate on a second installation member through a projection optical system, the inspection method comprises disposing an inspection photosensitive substrate as the substrate on the second installation member, illuminating a first region which doesn't include a pupil end of the projection optical system and a second region which includes the pupil end of the projection optical system and which isn't overlapped with the first region, in a state in which a surface of the photosensitive substrate and a surface of a secondary light source of the illumination optical system are optically conjugate with each other, and inspecting an illumination axis offset of the exposure apparatus based on a pattern obtained by developing the photosensitive substrate.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Soichi Inoue
  • Publication number: 20070236691
    Abstract: An inspection method for an exposure apparatus for illuminating a photomask on a first installation member by an illumination optical system, and for projecting an image of a pattern of the photomask onto a substrate on a second installation member through a projection optical system, the inspection method comprises disposing an inspection photosensitive substrate as the substrate on the second installation member, illuminating a first region which doesn't include a pupil end of the projection optical system and a second region which includes the pupil end of the projection optical system and which isn't overlapped with the first region, in a state in which a surface of the photosensitive substrate and a surface of a secondary light source of the illumination optical system are optically conjugate with each other, and inspecting an illumination axis offset of the exposure apparatus based on a pattern obtained by developing the photosensitive substrate.
    Type: Application
    Filed: June 5, 2007
    Publication date: October 11, 2007
    Inventors: Kazuya Fukuhara, Soichi Inoue
  • Publication number: 20070234269
    Abstract: A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape distribution of an effective light source is defined includes extracting plural point light sources from a shape distribution of the effective light source, entering the light emitted from each of the plural point light sources onto the pattern of the photomask, calculating an effective shape for each of the plural point light sources, the effective shape being a pattern obtained by excluding a part which is not irradiated with the light directly due to a sidewall of a pattern film including the pattern from a design shape of an aperture of the pattern, and calculating a distribution of diffraction light generated in the pattern for each of the plural point light sources by using the effective shape.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 4, 2007
    Inventors: Satoshi Tanaka, Shoji Mimotogi, Takashi Sato, Soichi Inoue
  • Publication number: 20070177127
    Abstract: There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 2, 2007
    Inventors: Tadahito Fujisawa, Soichi Inoue, Makoto Kobayashi, Masashi Ichikawa, Tsuneyuki Hagiwara, Kenichi Kodama
  • Publication number: 20070177126
    Abstract: There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 2, 2007
    Inventors: Tadahito Fujisawa, Soichi Inoue, Makoto Kobayashi, Masashi Ichikawa, Tsuneyuki Hagiwara, Kenichi Kodama
  • Patent number: 7248349
    Abstract: There is disclosed an exposure method for correcting a focal point, comprising: illuminating a mask, in which a mask-pattern including at least a set of a first mask-pattern and a second mask-pattern mutually different in shape is formed, from a direction in which a point located off an optical axis of an exposure apparatus is a center of illumination, and exposing and projecting an image of said mask-pattern toward an image-receiving element; measuring a mutual relative distance between images of said first and second mask-patterns exposed and projected on said image-receiving element, thereby measuring a focal point of a projecting optical system of said exposure apparatus; and moving said image-receiving element along a direction of said optical axis of said exposure apparatus on a basis of a result of said measurement, and disposing said image-receiving element at an appropriate focal point of said projecting optical system.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Sato, Shoji Mimotogi, Takahiro Ikeda, Soichi Inoue
  • Patent number: 7230680
    Abstract: There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: June 12, 2007
    Assignees: Kabushiki Kaisha Toshiba, Shin-Etsu Handotai Co., Ltd., Nikon Corporation
    Inventors: Tadahito Fujisawa, Soichi Inoue, Makoto Kobayashi, Masashi Ichikawa, Tsuneyuki Hagiwara, Kenichi Kodama
  • Publication number: 20070105391
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section. (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Application
    Filed: December 22, 2006
    Publication date: May 10, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Patent number: 7208423
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Publication number: 20070071306
    Abstract: An inspection method, includes obtaining a first optical characteristic of a projection optical system by transferring an image of an aberration measurement unit of a photomask on a first resist film coated on a first wafer by use of a first polarized exposure light; obtaining a second optical characteristic of the projection optical system by transferring the image of the aberration measurement unit on a second resist film coated on a second wafer by use of a second exposure light having a polarization state different from the first exposure light; and calculating a difference between the first and second optical characteristics.
    Type: Application
    Filed: November 30, 2006
    Publication date: March 29, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7194704
    Abstract: There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Shigeki Nojima, Suigen Kyoh, Kyoko Izuha, Ryuji Ogawa, Satoshi Tanaka, Soichi Inoue, Hirotaka Ichikawa
  • Patent number: 7186485
    Abstract: An inspection method, includes obtaining a first optical characteristic of a projection optical system by transferring an image of an aberration measurement unit of a photomask on a first resist film coated on a first wafer by use of a first polarized exposure light; obtaining a second optical characteristic of the projection optical system by transferring the image of the aberration measurement unit on a second resist film coated on a second wafer by use of a second exposure light having a polarization state different from the first exposure light; and calculating a difference between the first and second optical characteristics.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: March 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7181707
    Abstract: Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: February 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Koji Hashimoto, Soichi Inoue, Ichiro Mori
  • Patent number: 7148138
    Abstract: A method of forming a contact hole on a substrate by using a projection aligner comprising a lighting system including a light source, an aperture, and a condenser lens, a photo mask on which light from the lighting system is incident, and a projection lens for projecting the light from the photo mask onto the substrate, comprises forming a first photosensitive resist film on the substrate; exposing the first photosensitive resist film by using a photo mask in which mask patterns are cyclically arranged in a first direction and a second direction which is orthogonal to the first direction and a first aperture having light transmission parts arranged symmetrically with respect to a center point in the first direction; developing the exposed first photosensitive resist film to form first lines and linear spaces; forming a second photosensitive resist film on the substrate; exposing the second photosensitive resist film by using the photo mask and a second aperture having light transmission parts arranged symmet
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: December 12, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Mimotogi, Hiroko Nakamura, Kazuya Fukuhara, Satoshi Tanaka, Soichi Inoue