Patents by Inventor Soichi Inoue

Soichi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6249900
    Abstract: In a method of designing an LSI pattern, before pattern designing, the length B and line width W of a rectangle obtained by dividing a bent design pattern are used as parameters. A line width C at which a desired line width W is obtained for the length B of the rectangle is determined to be a correction value. Each correction value is listed in a table. In designing a pattern, the upper limit Bmax of the length of a line segment is first determined. Of the line segments of the bent design pattern, a shorter one than the upper limit Bmax is extracted. Then, a rectangle including the extracted line segment is extracted. Thereafter, the line width W of the extracted rectangle is corrected to the line width C by reference to the table.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: June 19, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Shoji Mimotogi, Soichi Inoue, Kazuko Yamamoto
  • Patent number: 6245466
    Abstract: A rectangular supplemental pattern having two edges of dimensions s1 and s2 is added to a main pattern corresponding to a design pattern. Where a change amount of shortening with respect to small changes &Dgr;s1 and &Dgr;s2 of the plan shape of the supplemental pattern, the plan shape of the supplemental pattern is determined such that the change amount s′={(±&Dgr;x/±&Dgr;s1)2+(±&Dgr;x/±&Dgr;s1)2}½ of the pattern plan shape on a wafer after transfer becomes a predetermined value or less.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: June 12, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 6226074
    Abstract: An exposure monitor mask used with an exposure system for manufacturing ICs includes an exposure detecting pattern having at least three patterns arranged in one direction, the exposure detecting pattern including a pair of relative position detecting patterns with at least one variable intensity pattern that allows the intensity of light transmitted therethrough to vary monotonously in the one direction disposed between the pair of relative position detecting patterns.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: May 1, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahito Fujisawa, Soichi Inoue, Hiroshi Nomura, Ichiro Mori
  • Patent number: 6221539
    Abstract: All edge positions constituting a first mask pattern are shifted by a predetermined change amount, to obtain a second mask pattern. A first finished plan shape transferred by the fist mask pattern and a second finished plan shape transferred by the second mask pattern are obtained by a calculation. Coefficients, which are obtained by respectively dividing dimensional differences between the edge positions of the first and second finished plan shapes by the change amount, are respectively calculated and assigned for edges. A corrected pattern is prepared by shifting the edge positions of the first mask pattern in accordance with magnitude of division of differences between a design pattern and the first finished plan shape by the coefficients assigned to the edges.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 6180293
    Abstract: A method for preparing a mask pattern used for forming a desired pattern on a substrate to be exposed comprises the steps of effecting correction on design data in connection with a first element to be corrected, the first element allowing a correction amount to be determined depending upon a pattern contained in an area of a predetermined size, converting the corrected design data to mask writing data, and when write processing is done with a writing device in which mask writing data is incorporated, effecting correction in connection with a second element to be corrected which excludes the first element.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: January 30, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tanaka, Toshiya Kotani, Soichi Inoue
  • Patent number: 6165652
    Abstract: A method of forming a photomask of a semiconductor device comprising the steps of forming a photosensitive film on a substrate and exposing the photosensitive film on the substrate by radiating with a radiation beam a plurality of butting unit regions defining butting portions between the butting unit regions and controlling said radiating of the butting unit region so that the butting portions of the butting unit regions are formed only in portions corresponding to isolation regions or alternatively, they are not formed in portions corresponding to contact areas.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Patent number: 6159642
    Abstract: An exposure mask includes a transparent substrate having a light shielding pattern and an aperture pattern thereon for transmitting an exposure light and arranged in that any two adjacent apertures of the same pattern size in the aperture pattern are different from each other in the etched depth, wherein a difference between the aperture pattern size and its adjacent light shielding pattern size, and the trench depth in the aperture pattern are determined by a sum of the aperture pattern size and its adjacent light shielding pattern size.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: December 12, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Satoshi Tanaka, Soichi Inoue, Hideki Kanai, Ikuo Yoneda
  • Patent number: 6110647
    Abstract: A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: August 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Hisashi Kaneko, Masahiko Hasunuma, Takamasa Usui, Masami Aoki, Kazuko Yamamoto, Sachiko Kobayashi
  • Patent number: 6107013
    Abstract: An exposure method includes the phase-shifting mask supply step, the phase-shifting mask being prepared by selectively forming a light-shielding portion and a phase shifter on a substrate, and the resist exposure step of performing both exposure of a resist by dark field illumination light and exposure of the resist by bright field illumination light by using the phase-shifting mask, thereby removing residual resist generated by the influence of the edge of the phase shifter.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: August 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahito Fujisawa, Satoshi Tanaka, Akiko Mimotogi, Shoji Mimotogi, Soichi Inoue
  • Patent number: 6077310
    Abstract: Pattern data that is an object of correction is divided into an area on which correction is made using correction values that have been obtained in advance for patterns and their respective layouts and an area on which correction is made on the basis of correction values calculated by a simulator. For example, simulation-based correction is made on a gate layer in a memory, while rule-based correction is made on a gate layer in the other area than the memory on the basis of rules for active gate width only. After being subjected to the correction, the areas are combined.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: June 20, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuko Yamamoto, Sachiko Miyama, Kiyomi Koyama, Soichi Inoue
  • Patent number: 6060368
    Abstract: This invention is provided to eliminate the optical proximity effect which will occur because of different rates of dimensional change between before and after etching when a plurality of gate materials are etched in a single device. After a to-be-corrected region is extracted, an n.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the n.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be a p.sup.+ -type polysilicon gate layer, thereby correcting the size of the n.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the n.sup.+ -type polysilicon gate layer. After that, a p.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the p.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be an n.sup.+ -type polysilicon gate layer, thereby correcting the size of the p.sup.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Hisako Aoyama, Soichi Inoue, Kazuko Yamamoto, Sachiko Kobayashi
  • Patent number: 6045981
    Abstract: A method of manufacturing a semiconductor device, which comprises the steps of, selectively silylating a photosensitive resin film by exposing the photosensitive resin film according to an exposure pattern thereby to form a silylated portion having a glass transition temperature which is lower than that of the photosensitive resin film and at the same time exposing the photosensitive resin film to an intermediate temperature between the glass transition temperature of the silylated portion and the glass transition temperature of the photosensitive resin film thereby fluidizing the silylated portion so as to cover a portion of the photosensitive resin film neighboring the silylated portion with the fluidized silylated portion, and developing the photosensitive resin film by making use of the silylated portion and the portion of photosensitive resin film covered by the fluidized silylated portion as a mask.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: April 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Akiko Mimotogi, Shoji Mimotogi, Soichi Inoue
  • Patent number: 6040114
    Abstract: A method of forming a pattern for a semiconductor device comprises the steps of forming a photosensitive film on a substrate and radiating the photosensitive film on the substrate with a beam of a predetermined shape consisting of one of a charged particle beam and an electromagnetic beam, thereby forming an exposed region of a desired shape, the latter step including the step of exposing each of unit regions by a single shot of the beam of the predetermined shape for a predetermined period of time, repeating the exposure a plurality of times, and butt-joining the exposed unit regions to thereby form the exposed region of the desired shape, wherein, in the step of forming the exposed region of the desired shape, butting portions of the unit regions are situated in a first area of a layer to be formed other than a second area in the layer in which predetermined characteristics of a function of the semiconductor device are determined by a pattern width of the exposed region in association with another pattern f
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: March 21, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Patent number: 5889678
    Abstract: In a topography simulation method, the topography of a resist pattern after curing treatment can be precisely estimated without producing a complex physical model or performing parameter measurement. Specifically, in the method of estimating the topography of a resist pattern, which is formed by selectively removing a part of a resist provided on a substrate and contracts due to curing treatment, the resist pattern is divided into a plurality of cells and the cells are contracted in accordance with a volume shrinkage amount per unit volume of the resist in the curing treatment. Then, the cells located closer to an interface between the substrate and the resist pattern are flattened to a higher degree in parallel to the substrate, and the deformed cells are brought together toward a shrinkage reference line passing through a center of a line pattern and toward the substrate.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Satoshi Tanaka, Shoji Mimotogi, Yasunobu Onishi
  • Patent number: 5889686
    Abstract: A profile of a developed resist is exactly simulated irrespective of whether or not a resist pattern is dense. A dissolution rate of a film to be processed, which film is provided on a substrate, is varied in accordance with a concentration of a developer and the profile of the developed resist is simulated with use of the varied dissolution rate. In addition, a spatial average of an optical image of a resist, which is averaged in the thickness direction of the resist, is calculated and the dissolution rate of the resist is modulated by using the calculated spatial average. The profile of the resist is simulated by using the modulated dissolution rate. Therefore, the profile of the resist on the substrate, which profile varies when the resist is exposed in a desired pattern and developed, can be exactly estimated.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Mimotogi, Soichi Inoue
  • Patent number: 5879844
    Abstract: Pattern data that is an object of correction is divided into an area on which correction is made using correction values that have been obtained in advance for patterns and their respective layouts and an area on which correction is made on the basis of correction values calculated by a simulator. For example, simulation-based correction is made on a gate layer in a memory, while rule-based correction is made on a gate layer in the other area than the memory on the basis of rules for active gate width only. After being subjected to the correction, the areas are combined.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuko Yamamoto, Sachiko Miyama, Kiyomi Koyama, Soichi Inoue
  • Patent number: 5876885
    Abstract: The profile simulation method of predicting a processed profile of a surface of a substrate to be changed by physically or chemically processing a film on the substrate to be processed comprises a step of changing a processing speed in correspondence with a convex portion and a recessed portion of the film on the substrate.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: March 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Mimotogi, Soichi Inoue, Akiko Mimotogi
  • Patent number: 5866280
    Abstract: An exposure mask comprises a phase shift section including a plurality of opening patterns formed by making openings in part of a shading film provided on a transmissive substrate and digging part of the substrate, and a non-phase shift section including at least one opening pattern. The opening pattern of the non-phase shift section has a dig whose amount of digging has been adjusted according to the amount of digging in the opening patterns of the phase shift section.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Kenji Kawano, Soichi Inoue, Satoshi Tanaka
  • Patent number: 5861866
    Abstract: An intensity distribution display method of displaying a intensity distribution of electromagnetic waves or charged particle beams fallen on a sample, is characterized by comprising the step of displaying the intensity distribution with the use of contour lines defined by Ie/(1+a.multidot.n/100), where Ie is a desired intensity value, a is a constant rate (%), and n is an integer.
    Type: Grant
    Filed: March 13, 1997
    Date of Patent: January 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Satoshi Tanaka
  • Patent number: 5783336
    Abstract: A mask for exposure includes a light transmitting substrate, a plurality of substantially oblong, island-like light transmitting sections arranged periodically on the substrate, an opaque section formed on the substrate except where the light transmitting sections are arranged, and a plurality of phase shifter layers selectively formed in the light transmitting sections. The light transmitting sections include paired light transmitting sections opposed to each other at one end portion, and one of the phase shifter layers is formed in one of the paired light transmitting sections. An interval between the paired light transmitting sections at one end portion is smaller than an interval between adjacent ones of the light transmitting sections at portions other than the one end portion.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: July 21, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masami Aoki, Yusuke Kohyama, Soichi Inoue, Akiko Nikki