Patents by Inventor Soichi Inoue

Soichi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020160277
    Abstract: There is provided a method which forms master masks used when a pattern of size larger than a region which can be exposed at one time is exposed on a to-be-exposed object. The pattern of the size larger than the region which can be exposed at one time is divided into a region of low repetitiveness and a region of high repetitiveness. A pattern of the region of low repetitiveness is drawn on at least one first master mask. Further, a pattern of the region of high repetitiveness is drawn on at least one second master mask.
    Type: Application
    Filed: April 9, 2002
    Publication date: October 31, 2002
    Inventors: Suigen Kyoh, Soichi Inoue
  • Publication number: 20020160590
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 31, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Publication number: 20020159049
    Abstract: There is disclosed a measuring method of illuminance unevenness of an exposure apparatus in which the illuminance unevenness resulting from a projection optical system, to project the light passed through the photomask onto the finite area on the photosensitive substrate via the projection optical system and to expose the photomask to the light, the method comprising calculating an average value of transmittance of the projection optical system of each path of the light emitted from one point of the photomask and reaching an imaging point for each of a plurality of imaging points in the finite area on the photosensitive substrate, and calculating the illuminance unevenness in the finite area on the photosensitive substrate from the average value of the transmittance obtained for each imaging point.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 31, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Sato, Soichi Inoue, Satoshi Tanaka
  • Publication number: 20020160279
    Abstract: In a pattern forming method, a cell pattern of each of memory cells is separated into a first pattern group provided at a predetermined position inside from an endmost portion of a cell and a second pattern group excluding the first pattern group. A mask size of the second pattern group is determined such that the second pattern group secures a sufficient process margin relative to a given size and size accuracy. A mask size of the first pattern group is optimized according to a peripheral pattern environment such that the first pattern group has a desired size under the above condition. A mask pattern of the memory cell is formed according to the mask size of the second pattern group and the first pattern group. The cell pattern is formed on a semiconductor wafer, using the mask pattern.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 31, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Publication number: 20020157083
    Abstract: An exposure mask pattern correction method comprises preparing a unit process group which includes a plurality of unit processes to form a pattern on a substrate by using an exposure mask, the plurality of unit processes including a unit process concerning manufacture of the exposure mask, a unit process concerning lithography using the exposure mask, and a unit process concerning etching of the substrate, setting a correction rule/model to perform an optical proximity effect correction for the exposure mask by using first and second optical proximity effects data when a change is arisen in at least one of the plurality of unit processes, the first and second optical proximity effect data being data respectively concerning an optical proximity effect caused by the at least one unit process before and after the change, and performing the optical proximity effect correction for the exposure mask by using the correction rule/model.
    Type: Application
    Filed: April 23, 2002
    Publication date: October 24, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Hashimoto, Soichi Inoue, Satoshi Tanaka, Satoshi Usui
  • Patent number: 6440616
    Abstract: There is disclosed a focus-monitoring mask which is adapted to be employed on an occasion of transferring a pattern on a wafer by way of photolithography, the mask comprising a first pattern region having at least one first monitor pattern which is constituted by a first opening surrounded by a first film or constituted by the first film surrounded by the first opening, and a second pattern region having at least one second monitor pattern which is constituted by a second opening surrounded by a second film or constituted by the second film surrounded by the second opening, and is capable of giving a predetermined phase difference to an exposure light passing through the second film relative to an exposure light passing through the second opening, wherein the first and second monitor patterns have a configuration in which both ends thereof are tapered from a central portion thereof.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: August 27, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoko Izuha, Tadahito Fujisawa, Soichi Inoue
  • Publication number: 20020100012
    Abstract: According to a focus monitoring method, an exposure mask on which a focus monitor pattern comprising at least two types of pattern groups is formed is prepared. A pattern group A of the at least two pattern groups is illuminated with illumination light while a barycenter of an illumination light source of illumination optics is in an off-axis state. At least a pattern group B of the at least two pattern groups is illuminated with illumination light while the barycenter of the illumination light source is in an on-axis state. A positional deviation between the pattern groups A and B transferred onto a substrate is measured. An effective focus position can be monitored from this positional deviation.
    Type: Application
    Filed: January 23, 2002
    Publication date: July 25, 2002
    Inventors: Takumichi Sutani, Tadahito Fujisawa, Takashi Sato, Takashi Sakamoto, Masafumi Asano, Soichi Inoue
  • Patent number: 6423977
    Abstract: A pattern size evaluation apparatus comprising an illumination optical system for projecting parallel light rays of a predetermined wavelength on a monitoring area formed on an object, the monitoring area being formed at a position different from a device pattern formed on the object, a light intensity detection optical system for detecting diffracted light from the monitoring area, and a device pattern size evaluation section for evaluating a size of the device pattern based on an intensity of diffracted light from the monitoring area.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: July 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito, Kenji Kawano, Soichi Inoue, Katsuya Okumura
  • Patent number: 6376139
    Abstract: A control method for an exposure apparatus, in which an exposure amount and a focus value are set in transferring a circuit pattern on a mask onto a resist formed on a wafer by the exposure apparatus, includes the steps of arranging, on the mask, an exposure amount monitor mark and a focus monitor mark used to separately monitor the effective exposure amount and the focus value on the wafer, transferring the exposure amount monitor mark and the focus monitor mark onto the resist to form an exposure amount monitor pattern and a focus monitor pattern, measuring the states of the exposure amount monitor pattern and the focus monitor pattern at least at one of timings after exposure, after post exposure baking, during a cooling process after baking, during a process after cooling, during development, and after development, on the basis of the measurement results, calculating the difference between an optimum exposure amount value and an exposure amount set value set in the exposure apparatus and the difference be
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: April 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahito Fujisawa, Soichi Inoue, Kenji Kawano, Shinichi Ito, Ichiro Mori
  • Publication number: 20020045132
    Abstract: A method of forming a pattern for a semiconductor device comprises the steps of forming a photosensitive film on a substrate and radiating the photosensitive film on the substrate with a beam of a predetermined shape consisting of one of a charged particle beam and an electromagnetic beam, thereby forming an exposed region of a desired shape, the latter step including the step of exposing each of unit regions by a single shot of the beam of the predetermined shape for a predetermined period of time, repeating the exposure a plurality of times, and butt-joining the exposed unit regions to thereby form the exposed region of the desired shape, wherein, in the step of forming the exposed region of the desired shape, butting portions of the unit regions are situated in a first area of a layer to be formed other than a second area in the layer in which predetermined characteristics of a function of the semiconductor device are determined by a pattern width of the exposed region in association with another pattern f
    Type: Application
    Filed: December 10, 2001
    Publication date: April 18, 2002
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Patent number: 6340542
    Abstract: A method of manufacturing a semiconductor device, light is applied through the cell patterns made in master masks, thereby transferring the cell patterns to, and forming the cell patterns on, a wafer. On the basis of layout data representing a layout diagram of the semiconductor device, the pattern data of the device is divided along the boundaries of the function blocks of the device, generating pattern data items. Master masks are prepared in accordance with the pattern data items. Light is applied to the wafer, first through the master mask and then through the master mask. The cell patterns made in the master masks are transferred to the wafer.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: January 22, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Suigen Kyoh, Iwao Higashikawa, Ichiro Mori
  • Publication number: 20020002697
    Abstract: A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
    Type: Application
    Filed: June 28, 2001
    Publication date: January 3, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 6335145
    Abstract: A method of forming a pattern for a semiconductor device comprises the steps of forming a photosensitive film on a substrate and radiating the photosensitive film on the substrate with a beam of a predetermined shape consisting of one of a charged particle beam and an electromagnetic beam, thereby forming an exposed region of a desired shape, the latter step including the step of exposing each of unit regions by a single shot of the beam of the predetermined shape for a predetermined period of time, repeating the exposure a plurality of times, and butt-joining the exposed unit regions to thereby form the exposed region of the desired shape, wherein, in the step of forming the exposed region of the desired shape, butting portions of the unit regions are situated in a first area of a layer to be formed other than a second area in the layer in which predetermined characteristics of a function of the semiconductor device are determined by a pattern width of the exposed region in association with another pattern f
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: January 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Publication number: 20010055720
    Abstract: When an alignment mark and first and second overlay deviation inspection marks as well as a device pattern are successively formed on a wafer using a first photomask and a second photomask, each of the alignment mark and the overlay deviation inspection marks are formed to have a part of the device pattern or marks having sizes and shapes similar to those of the device pattern, whereby these marks receive a deviation error caused by the influence given by the aberration of the light projection optical lens used for performing the pattern transfer and an error in the following processing steps in substantially the same degree as the device pattern, and an amount of the overlay deviation error is measured correctly so as to achieve an alignment of the photomasks in a high accuracy.
    Type: Application
    Filed: June 7, 2001
    Publication date: December 27, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Sato, Soichi Inoue
  • Patent number: 6317198
    Abstract: In a method of examining the shape of the light source of an exposure tool, the shape of the pupil of its projection optical system, and the alignment of the shape of the light source with the shape of the pupil, the exposure tool comprising a light source, an illumination optical system for directing the light emitted from the light source to a reticle, and a projection optical system for transferring the reduced image on the reticle onto a wafer, the light emitted from the light source is projected on a reticle including a grating pattern where a transmitting area and a shading area are repeated in a finite number, the diffracted light of the first order or higher passed through the reticle is caused to illuminate the outer edge of the pupil of the projection optical system, and the pattern image on the reticle is projected on the wafer in the defocus state.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: November 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Sato, Satoshi Tanaka, Tadahito Fujisawa, Soichi Inoue
  • Patent number: 6316163
    Abstract: A method for forming patterns, in which pattern transfer to the same photosensitive material on a first layer is carried out using both light exposure and charged particle beam exposure, comprises the steps of performing a predetermined geometric operation between data associated with a pattern to be transferred to the first layer and data associated with a pattern to be transferred to a second layer different from the first layer, separating the pattern data associated with the pattern to be transferred to the first layer into first exposure pattern data for charged particle beam exposure and second exposure pattern data for light exposure, and performing pattern transfer on to the first layer based on the result of the separation.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: November 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunko Magoshi, Masamitsu Itoh, Shinji Sato, Soichi Inoue, Kazuyoshi Sugihara, Katsuya Okumura
  • Publication number: 20010019407
    Abstract: Light emitted from an illumination optical system is guided to a photomask where a pattern is formed of an optical member including a light transmission pattern as a diffraction grating pattern, in which a light transmission part and a opaque part are repeated in a finite period and a periphery of the light transmission pattern is shielded by a opaque area, such that a plurality of ratios are given between the light transmission part and the opaque part. Diffraction light, which has passed through the photomask, is irradiated on a projection optical system, thereby to transfer a pattern reflecting an intensity distribution of the diffraction light to a wafer. A change of transmittance depending on a light path of the projection optical system is measured, based on a pattern image of the diffraction light transferred to the wafer. Pattern transfer is carried out in a non-conjugate state.
    Type: Application
    Filed: February 15, 2001
    Publication date: September 6, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Sato, Soichi Inoue
  • Publication number: 20010005566
    Abstract: A mask pattern correction method includes the step of extracting a correction target edge from a design pattern, the step of calculating the distance from the correction target edge to the nearest edge of an adjacent pattern, the step of calculating the correction value by a simulation in accordance with a pattern layout present within a given range determined by the correction target edge, and moving the correction target edge on the basis of the calculated correction value when the distance calculated in the distance calculation step is smaller than a predetermined distance, and the step of moving the correction target edge on the basis of an correction value set as a rule in advance in accordance with the distance when the distance calculated in the distance calculation step is larger than the predetermined distance.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 6252651
    Abstract: An exposure method includes the phase-shifting mask supply step, the phase-shifting mask being prepared by selectively forming a light-shielding portion and a phase shifter on a substrate, and the resist exposure step of performing both exposure of a resist by dark field illumination light and exposure of the resist by bright field illumination light by using the phase-shifting mask, thereby removing residual resist generated by the influence of the edge of the phase shifter.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: June 26, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahito Fujisawa, Satoshi Tanaka, Akiko Mimotogi, Shoji Mimotogi, Soichi Inoue
  • Patent number: 6251544
    Abstract: In an exposure dose measuring method for measuring an effective exposure dose on a wafer by printing mask patterns formed on a mask onto a resist coated on the wafer by exposure, each of the mask patterns has light transmitting sections and light shielding sections repeated in a period p, a ratio of areas of the light transmitting sections to areas of the light shielding sections of each of the mask patterns differs from ratios of those of the others of the mask patterns, and the period p is set so as to satisfy a relationship of p/M≦&lgr;/(1+&sgr;)NA, where an exposure light wavelength at the time of exposing the mask patterns is &lgr;, a numerical aperture at a wafer side is NA, an illumination coherence factor is &sgr;, and a mask pattern magnification for patterns to be formed on the wafer is M.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: June 26, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Shinichi Ito, Kei Hayasaki