Abstract: A variable resistance memory device includes a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer and protecting the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction parallel with the channel layer. The capping layer may maintain oxygen vacancies formed in the variable resistance layer.

Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

Abstract: A variable resistance memory device includes a variable resistance layer and a first conductive element and a second conductive element which are spaced apart from each other on the variable resistance layer. The variable resistance layer may include a first layer and a second layer on the first layer. The first layer includes a ternary or more metal oxide containing two or more metal materials having different valences. The second layer may include silicon oxide. The variable resistance memory device may have a wide range of resistance variation due to the metal oxide in which oxygen vacancies are easily formed. The first conductive element and the second conductive element, in response to an applied voltage, may be configured to form a current path in a direction perpendicular to a direction in which the first layer and the second direction are stacked.

Abstract: A variable resistance memory device includes a first conductive line extending in a first direction, a second conductive line extending in a second direction, the second direction intersecting the first direction on the first conductive line, a fixed resistance layer between the first conductive line and the second conductive line, and a variable resistance layer between the first conductive line and the second conductive line, wherein the fixed resistance layer and the variable resistance layer are electrically connected in parallel to each other between the first conductive line and the second conductive line.

Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: A planar heating apparatus includes a substrate, first electrodes on the substrate, second electrodes alternately arranged with the first electrodes, an electrode connector connecting end portions of the first or second electrodes to each other and a power connector connected to the electrode connector and to which a power supply is connected. The power connector extends outside of the substrate.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: A vertical nonvolatile memory device including a memory cell string using a resistance change material is disclosed. Each memory cell string of the nonvolatile memory device includes a semiconductor layer extending in a first direction and having a first surface opposite a second surface, a plurality of gates and a plurality of insulators alternately arranged in the first direction and extending in a second direction perpendicular to the first direction, a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a dielectric film extending in the first direction on the surface of the semiconductor layer and having a plurality of movable oxygen vacancies distributed therein.

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

Abstract: A nonvolatile memory cell resistance change type nonvolatile memory cell configured to store information by changing an electrical resistance according to application of electrical stress is provided and a nonvolatile memory device including the nonvolatile memory cell is provided. The resistance change type nonvolatile memory cell includes a resistance change material layer including a resistance change material; a ferroelectric layer on a first side of the resistance change material layer, the ferroelectric layer configured to change an electrical resistance of the resistance change material layer according to a polarization direction and polarization size of a ferroelectric therein; a first electrode on the ferroelectric layer and configured to control the polarization direction and the polarization size of the ferroelectric based on an applied voltage; and a second electrode and a third electrode on the resistance change material layer with the first electrode therebetween.

Abstract: A nonvolatile memory cell resistance change type nonvolatile memory cell configured to store information by changing an electrical resistance according to application of electrical stress is provided and a nonvolatile memory device including the nonvolatile memory cell is provided. The resistance change type nonvolatile memory cell includes a resistance change material layer including a resistance change material; a ferroelectric layer on a first side of the resistance change material layer, the ferroelectric layer configured to change an electrical resistance of the resistance change material layer according to a polarization direction and polarization size of a ferroelectric therein; a first electrode on the ferroelectric layer and configured to control the polarization direction and the polarization size of the ferroelectric based on an applied voltage; and a second electrode and a third electrode on the resistance change material layer with the first electrode therebetween.

Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.

Abstract: Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array having a vertically stacked structure, a bit line for applying a programming voltage to the memory cell array, and a control logic. The memory cell array includes memory cells that each include a corresponding portion of a semiconductor layer and a corresponding portion of a resistance layer. The memory cells include a non-selected memory cell, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell, based on applying a first voltage to the compensation memory cell, a second voltage to the selected memory cell, and a third voltage to the non-selected memory cell. The adjusted program voltage may be dropped compared to the programming voltage due to the compensation memory cell.

Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.

Abstract: Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array having a vertically stacked structure, a bit line for applying a programming voltage to the memory cell array, and a control logic. The memory cell array includes memory cells that each include a corresponding portion of a semiconductor layer and a corresponding portion of a resistance layer. The memory cells include a non-selected memory cell, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell, based on applying a first voltage to the compensation memory cell, a second voltage to the selected memory cell, and a third voltage to the non-selected memory cell. The adjusted program voltage may be dropped compared to the programming voltage due to the compensation memory cell.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: Provided is a non-volatile memory device including a control logic, a semiconductor layer, a resistance switching layer, a gate oxide layer, and a gate stack including a plurality of gates and a plurality of insulating layers, wherein the plurality of gates and the plurality of insulating layers are stacked alternately with each other. The resistance switching layer is provided between the semiconductor layer and the gate stack. The gate oxide layer is provided between the resistance switching layer and the gate stack. A cell string including a plurality of memory cells is formed by the gate stack, the resistance switching layer, and the gate oxide layer.

Abstract: A composition for forming a heating element; a dried and sintered product thereof; and a method of preparing the composition for forming a heating element, the composition including a matrix particle, a composite filler, and a solvent, wherein the composite filler includes a core and a coating layer disposed on the core, the core includes a nanosheet filler, and the composition has a pH in a range of about 5 to about 9.