Patents by Inventor Somnath Paul

Somnath Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10755771
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Patent number: 10748060
    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Publication number: 20200258890
    Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Charles AUGUSTINE, Somnath PAUL, Muhammad M. KHELLAH, Chen KOREN
  • Publication number: 20200183922
    Abstract: An apparatus is described. The apparatus includes a nearest neighbor search circuit to perform a search according to a first stage search and a second stage search. The nearest neighbor search circuit includes a first stage circuit and a second stage circuit. The first stage search circuit includes a hash logic circuit and a content addressable memory. The hash logic circuit is to generate a hash word from a input query vector. The hash word has B bands. The content addressable memory is to store hashes of a random access memory's data items. The hashes each have B bands. The content addressable memory is to compare the hashes against the hash word on a sequential band-by-band basis. The second stage circuit char the random access memory and a compare and sort circuit. The compare and sort circuit is to receive the input query vector. The random access memory has crosswise bit lines coupled to the compare and sort circuit.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Inventors: Wootaek LIM, Minchang CHO, Somnath PAUL, Charles AUGUSTINE, Suyoung BANG, Turbo MAJUMDER, Muhammad M. KHELLAH
  • Patent number: 10665222
    Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Suyoung Bang, Muhammad Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Wootaek Lim, Tobias Bocklet, David Pearce
  • Publication number: 20200133884
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a memory side cache and an NVRAM system memory. The memory controller has logic circuitry to favor items cached in the memory side cache that are expected to be written to above items cached in the memory side cache that are expected to only be read from.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 30, 2020
    Inventors: Zeshan A. CHISHTI, Somnath PAUL, Charles AUGUSTINE, Muhammad M. KHELLAH
  • Patent number: 10635968
    Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah, Sadique Ul Ameen Sheik
  • Patent number: 10586147
    Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 10, 2020
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Charles Augustine, Somnath Paul
  • Publication number: 20200005468
    Abstract: Methods, systems, and articles herein are directed to event-driven object segmentation to track events rather than tracking all pixel locations in an image.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Somnath Paul, Turbo Majumder, Mohamed Elmalaki, Muhammad Khellah, Charles Augustine
  • Patent number: 10489702
    Abstract: Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight memory.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Patent number: 10423203
    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Rafael Rios, Somnath Paul, Muhammad M. Khellah
  • Patent number: 10403266
    Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Muhammad Khellah, Oren Arad, Binuraj Ravindran, Somnath Paul, Charles Augustine, Bruno Umbria Pedroni
  • Publication number: 20190198093
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Publication number: 20190115011
    Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Applicant: Intel Corporation
    Inventors: Muhammad Khellah, Oren Arad, Binuraj Ravindran, Somnath Paul, Charles Augustine, Bruno Umbria Pedroni
  • Publication number: 20190043477
    Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Suyoung Bang, Muhammad Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Wootaek Lim, Tobias Bocklet, David Pearce
  • Publication number: 20190043583
    Abstract: Provided are an apparatus, video processing unit, and method for clustering events in a content addressable memory. An event is received including at least one parameter value and a timestamp. A determination is made as to whether there is a valid entry in the memory having at least one parameter value within a predefined range of values of the at least one parameter value in the event. In response to a determination that there is the valid entry, writing the at least one parameter value and the timestamp in the event to the valid entry.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 7, 2019
    Inventors: Turbo MAJUMDER, Somnath PAUL, Charles AUGUSTINE, Muhammad M. KHELLAH
  • Patent number: 10129219
    Abstract: Methods and systems for securing data are provided. For example, one method includes providing context information for an input/output (I/O) operation to a security module by an adapter communicating with a computing device and a storage device via a network; storing encryption parameters associated to a security association handle by the security module; using a workflow handle by the security module to obtain the security association handle for retrieving stored encryption parameters for encrypting payload transmitted by the adapter and for decrypting payload received by the adapter; predicting a first frame header for encrypting the payload transmitted by the adapter and a second frame header for decrypting payload received by the adapter; providing the encrypted payload for transmission to the adapter by the security module, after discarding the first predicted header; and providing the decrypted payload to the computing device by the security module, after discarding the second predicted header.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 13, 2018
    Assignee: Cavium, LLC
    Inventors: Somnath Paul, Bruce A. Klemin, Muralidhar Jammula
  • Publication number: 20180322384
    Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.
    Type: Application
    Filed: May 2, 2017
    Publication date: November 8, 2018
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Publication number: 20180181175
    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Charles Augustine, Rafael Rios, Somnath Paul, Muhammad M. Khellah
  • Patent number: 9953690
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah