Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes spiking neural network circuitry. The spiking neural network circuitry includes a learning rule circuit. The learning rule circuit includes a resistive element. A resistance of the resistive element is to determine a change in a weight of a synapse between neurons of the spiking neural network circuitry.

Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

Abstract: A network interface to transport a continuous datastream over a frame-based transport network. The network interface includes a data input, an egress buffer circuit, a phase locked loop, and a data output. The data input receives frames carrying the continuous datastream from the frame-based transport network. The egress buffer circuit is coupled to buffer the continuous datastream and to generate a feedback signal based at least in part on a fill-level of the egress buffer. The phase locked loop is coupled to receive the feedback signal from the egress buffer and to recover a clock signal from the continuous datastream. The data output is coupled to output the data of the continuous datastream from the egress buffer circuit based on the clock signal.

Abstract: A system (100) can update a network performance counter and include link layer (MAC blocks) devices (102-0 to 102-N) coupled in a daisy chain manner. A single performance counter (104) can serve all of the link layer devices (102-0 to 102-N), receiving statistics vectors from all link layer devices (102-0 to 102-N) and a vector enable signal from a last link layer device 102-N in the chain. A method (1200) for updating a performance counter according to such a daisy chain configuration is also disclosed.

Abstract: A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.

Abstract: Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers.

Abstract: A method and apparatus for performing byte rate adaptation. Specifically, embodiments of the present invention describe a method for deleting bytes when performing byte rate adaptation. The method begins by receiving data at a first rate. The data comprises valid data and deletable data. The data also comprises a plurality of cycles, wherein each cycle comprises a word length of W bytes. The method continues by compressing the plurality of cycles into a compressed cycle by deleting redundant deletable bytes. The compressed cycle comprises at least one valid data byte. Thereafter, the method substitutes remaining deletable bytes in the first compressed cycle with a uniform character, and sends the compressed cycle to a FIFO buffer for further transmission.

Abstract: Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

Abstract: Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.

Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Abstract: A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

Abstract: An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.

Abstract: An apparatus for providing arbitration for a dual-port memory. The apparatus may be configured to prevent a write cycle extension during contention between simultaneous read and write operations.