Patents by Inventor Somnath Paul

Somnath Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7138930
    Abstract: Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: November 21, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Somnath Paul, Hamid Khodabandehlou
  • Patent number: 7073019
    Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: July 4, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Amitabha Banerjee, Somnath Paul
  • Patent number: 7036037
    Abstract: A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: April 25, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Somnath Paul, Rakesh Mehrotra
  • Patent number: 7016349
    Abstract: An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: March 21, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Patent number: 6957309
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: October 18, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jay K. Gupta, Somnath Paul
  • Patent number: 6948030
    Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: September 20, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jay Kishora Gupta, Amitabha Banerjee, Somnath Paul
  • Patent number: 6925506
    Abstract: A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: August 2, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Patent number: 6816979
    Abstract: An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: November 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jiann-Cheng Chen, Somnath Paul, S. Babar Raza
  • Patent number: 6816955
    Abstract: An apparatus for providing arbitration for a dual-port memory. The apparatus may be configured to prevent a write cycle extension during contention between simultaneous read and write operations.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: November 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Patent number: 6810098
    Abstract: An apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: October 26, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Somnath Paul, S. Babar Raza
  • Patent number: 6760872
    Abstract: A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: July 6, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jay K. Gupta, Somnath Paul
  • Publication number: 20040117584
    Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.
    Type: Application
    Filed: December 11, 2002
    Publication date: June 17, 2004
    Inventors: Amitabha Banerjee, Somnath Paul
  • Patent number: 6721878
    Abstract: A method and processor configured to handle an exception may employ a “retry” signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an exception is to be serviced during a period in which the memory access is delayed. In one embodiment for which the exception is an interrupt, the retry signal is asserted when memory access is delayed and the processor may proceed to service an interrupt request during this period of delayed memory access, regardless of the degree of completion of an instruction by the processor. During a period of delayed memory access, the processor may suspend instruction execution until the memory access becomes available. Upon completion of servicing the interrupt, the processor may resume instruction execution beginning with the last instruction attempted before the suspension of the instruction execution due to the delayed memory access.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: April 13, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Somnath Paul, Gregory H. Efland
  • Patent number: 6715021
    Abstract: An apparatus comprising a plurality of storage devices and a scheduler circuit. Each of the plurality of storage devices may be configured to store and present one or more packets of a data stream over one or more first busses operating at a first speed. The scheduler circuit may be configured to determine which of the plurality of storage devices transmits the packets of the data stream. A second bus that may be configured to carry look ahead information and synchronize the plurality of devices. The second bus may operate at a second speed.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: March 30, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Somnath Paul, S. Babar Raza
  • Patent number: 6704863
    Abstract: A method, system and processor are provided for minimizing latency and loss of processor bandwidth in a pipelined processor when responding to an interrupt. The method advantageously avoids emptying and refilling the processor's instruction pipeline in order to service an interrupt request. Instead, a short sequence of instructions comprising the interrupt response is inserted into the pipeline. Normal pipeline operation stalls while the inserted instructions execute, but since flow is not disrupted the loss in bandwidth is not as great as if the pipeline were flushed. Furthermore, direct insertion of the instructions into the pipeline avoids the need for the processor to save its context and branch to an interrupt service routine in memory; this results in much faster response in servicing the interrupt, thereby reducing latency.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: March 9, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Somnath Paul, Gregory H. Efland
  • Patent number: 6631455
    Abstract: An apparatus for initializing a default value of a queue. The apparatus comprising a memory section having a first storage element and a second storage element. The apparatus may be configured to pass the default value and initialize the default value of the queue without writing to the memory section.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 7, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Patent number: 6629226
    Abstract: An interface coupled to a multiqueue storage device and configured to interface the multiqueue storage device with one or more handshaking signals. The multiqueue storage device and the interface may be configured to transfer variable size data packets.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 30, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Somnath Paul, S. Babar Raza
  • Patent number: 6625711
    Abstract: An apparatus comprising a plurality of devices configured to store and present data to a plurality of queues. Each of the plurality of devices may be configured to receive (i) one or more first control signals configured to control data transfer and (ii) one or more second control signals to configure the plurality of queues. A particular one or more of the plurality of devices may be selected in response to one or more device identification bits.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 23, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Patent number: 6581144
    Abstract: An apparatus for implementing memory initialization comprising a logic circuit configured to present an address to a memory. The memory initialization may occur as a background process.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 17, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul
  • Patent number: 6578118
    Abstract: A method for writing and reading in-band information to and from a single storage element, comprising the steps of (A) receiving the in-band information, (B) storing data in either (i) a port information register when in a first state or (ii) a memory element when in a second state and (C) storing subsequent data in the memory element. The first state and the second state may be dependent upon a block position of the in-band information.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 10, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: S. Babar Raza, Somnath Paul