Patents by Inventor Somnath Paul

Somnath Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180181175
    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Charles Augustine, Rafael Rios, Somnath Paul, Muhammad M. Khellah
  • Patent number: 9953690
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Publication number: 20180107922
    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Publication number: 20180107919
    Abstract: Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight memory.
    Type: Application
    Filed: December 6, 2016
    Publication date: April 19, 2018
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah
  • Publication number: 20180082176
    Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: Wei WU, Charles AUGUSTINE, Somnath PAUL
  • Publication number: 20170365313
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 21, 2017
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Publication number: 20170277628
    Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Somnath Paul, Charles Augustine, Muhammad M. Khellah, Sadique Ul Ameen Sheik
  • Patent number: 9734880
    Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik, Muhammad M. Khellah
  • Publication number: 20170083813
    Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes spiking neural network circuitry. The spiking neural network circuitry includes a learning rule circuit. The learning rule circuit includes a resistive element. A resistance of the resistive element is to determine a change in a weight of a synapse between neurons of the spiking neural network circuitry.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: CHARLES AUGUSTINE, SOMNATH PAUL
  • Publication number: 20160232051
    Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Somnath Paul, Sriram R. Vangal
  • Patent number: 9337952
    Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Sriram R. Vangal
  • Patent number: 8990662
    Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Somnath Paul, Sriram R. Vangal, Michael D. Abbott, Eugene M. Kishinevsky
  • Publication number: 20140317458
    Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 23, 2014
    Inventors: Somnath Paul, Sriram R. Vangal
  • Publication number: 20140095953
    Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: Somnath Paul, Sriram R. Vangal, Michael D. Abbott, Eugene M. Kishinevsky
  • Patent number: 8094562
    Abstract: A network interface to transport a continuous datastream over a frame-based transport network. The network interface includes a data input, an egress buffer circuit, a phase locked loop, and a data output. The data input receives frames carrying the continuous datastream from the frame-based transport network. The egress buffer circuit is coupled to buffer the continuous datastream and to generate a feedback signal based at least in part on a fill-level of the egress buffer. The phase locked loop is coupled to receive the feedback signal from the egress buffer and to recover a clock signal from the continuous datastream. The data output is coupled to output the data of the continuous datastream from the egress buffer circuit based on the clock signal.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jason Baumbach, Somnath Paul, Paul Scott
  • Patent number: 7512075
    Abstract: A system (100) can update a network performance counter and include link layer (MAC blocks) devices (102-0 to 102-N) coupled in a daisy chain manner. A single performance counter (104) can serve all of the link layer devices (102-0 to 102-N), receiving statistics vectors from all link layer devices (102-0 to 102-N) and a vector enable signal from a last link layer device 102-N in the chain. A method (1200) for updating a performance counter according to such a daisy chain configuration is also disclosed.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: March 31, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Somnath Paul, Hamid Khodabandehlou
  • Patent number: 7496109
    Abstract: A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: February 24, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jay K. Gupta, Somnath Paul
  • Patent number: 7379467
    Abstract: Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: May 27, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Somnath Paul, Sanjay Rekhi
  • Patent number: 7356044
    Abstract: A method and apparatus for performing byte rate adaptation. Specifically, embodiments of the present invention describe a method for deleting bytes when performing byte rate adaptation. The method begins by receiving data at a first rate. The data comprises valid data and deletable data. The data also comprises a plurality of cycles, wherein each cycle comprises a word length of W bytes. The method continues by compressing the plurality of cycles into a compressed cycle by deleting redundant deletable bytes. The compressed cycle comprises at least one valid data byte. Thereafter, the method substitutes remaining deletable bytes in the first compressed cycle with a uniform character, and sends the compressed cycle to a FIFO buffer for further transmission.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 8, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Somnath Paul, Gopal K. Garg
  • Patent number: 7272675
    Abstract: Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: September 18, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Somnath Paul, Sanjay Rekhi