Abstract: The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as network interface cards, audio cards, input/output cards, and the like, are allowed to participate on at least a limited basis in the coherency domain by having cache memory that duplicates a FIFO buffer in main memory used to exchange information between software and the hardware. To exchange information, software writes to the FIFO buffer which invalidates the data in the cache-type memory of the hardware device, and the invalidation message acts to notify the hardware device of the availability of information in the FIFO buffer.

Abstract: A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus access, and also receives a signal indicating the pending workload of that device, as measured by the number of operations pending in a queue in that device. Based on the workload signal, the bus arbiter breaks any arbitration conflicts by assigning priority to the device with the greatest workload. In the event of ties, the bus arbiter may use other arbitration schemes to break ties between devices with equal workloads.

Abstract: A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.

Abstract: A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in X4 and X8 memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. When operating in a X8 mode, all errors, including single-bit errors are corrected by the XOR memory engine. If more than one single bit error is detected on a single transaction, one or more of the errors may be corrected using ECC techniques.

Abstract: A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. If X16 or X32 memory devices are implemented, a technique for striping the data from each memory device is implemented to detect errors in the X16 and X32 devices.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port (“AGP”) bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table (“GART table”) is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: A new technique for transferring data between nodes of a clustered computing system is disclosed. In one aspect, the invention includes a cluster node comprising a system bus; a memory device; and an internodal interconnect. The internodal interconnect is electrically connected to the system bus and includes a remote connection port. The internodal interconnect is capable of transferring data from the memory device and through the remote connection port. In a second aspect, a the invention includes method for internodal data transfer in a clustered computing system. Each of at least two clusters includes an internodal interconnect electrically connected to a system bus and a memory device to the system bus. The method itself comprises requesting a data transfer and then transferring the requested data. The requested data is transferred from the memory device in a first cluster node to the memory device in a second cluster node via the internodal interconnects in the first and second cluster nodes.

Abstract: A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: A method for restoring resources on a computer is provided. The method includes providing a configuration database including resource information, receiving a restoration request including a computer identifier associated with the computer, accessing the configuration database based on the computer identifier to identify a restorable resource associated with the computer, and providing the restorable resource to the computer. A computer system includes a computer and a configuration manager. The computer has a plurality of installed resources. The configuration manager is coupled to the computer and adapted to store a configuration database including resource information associated with the computer, receive a restoration request from the computer including a computer identifier associated with the computer, access the configuration database to identify a restorable resource based on the computer identifier associated with the computer, and provide the restorable resource to the computer.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Abstract: A computer system and method of operating a network in which data overflow from workstation or PC hard drives is automatically transferred over to a network server hard drive allowing the workstation user to continue working without interruption. Furthermore, this system minimizes the amount of time a network administrator spends on attending to users who have no remaining hard drive space on their computers.

Abstract: A method for restoring resources on a computer is provided. The method includes providing a configuration database including resource information, receiving a restoration request including a computer identifier associated with the computer, accessing the configuration database based on the computer identifier to identify a restorable resource associated with the computer, and providing the restorable resource to the computer. A computer system includes a computer and a configuration manager. The computer has a plurality of installed resources. The configuration manager is coupled to the computer and adapted to store a configuration database including resource information associated with the computer, receive a restoration request from the computer including a computer identifier associated with the computer, access the configuration database to identify a restorable resource based on the computer identifier associated with the computer, and provide the restorable resource to the computer.

Abstract: A computer system includes a memory controller that controls and formats transactions with a high speed memory. The memory controller includes a read queue, a write queue, and various other queues in which memory transactions may be stored pending execution. The memory controller periodically executes calibration cycles, such as temperature calibration cycles to the memory to reduce memory errors. The temperature calibration cycles may include an idle state during which no read transactions can be executed. The memory controller includes arbitration logic that reduces latency by issuing read transaction first. Once reads have been issued, the arbitration logic executes any pending temperature cycles. During the idle period of the calibration cycle, the arbitration logic schedules write transactions, and transactions to memory from other queues and devices, including precharge transactions, row activate transactions, refresh cycles, and other calibration cycles.

Abstract: A computer system includes a plurality of field replaceable units, each having volatile memory and at least one CPU. The FRUs communicate with each other via centralized logic. A RAID data fault tolerance technique is applied to the system so that an FRU can be lost or removed without loss of its data. An exclusive OR engine is included in the centralized logic or distributed among the FRUs. The RAID logic can restripe itself upon removal or addition of a FRU.

Abstract: A computer system and method in which an electrically controlled “hoodlock,” which prevents the computer's chassis from unauthorized opening, can be remotely accessed through powerline communications.

Abstract: The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as network interface cards, audio cards, input/output cards, and the like, are allowed to participate on at least a limited basis in the coherency domain by having cache memory that duplicates a FIFO buffer in main memory used to exchange information between software and the hardware. To exchange information, software writes to the FIFO buffer which invalidates the data in the cache-type memory of the hardware device, and the invalidation message acts to notify the hardware device of the availability of information in the FIFO buffer.