Abstract: The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as network interface cards, audio cards, input/output cards, and the like, are allowed to participate on at least a limited basis in the coherency domain by having cache memory that duplicates a FIFO buffer in main memory used to exchange information between software and the hardware. To exchange information, software writes to the FIFO buffer which invalidates the data in the cache-type memory of the hardware device, and the invalidation message acts to notify the hardware device of the availability of information in the FIFO buffer.

Abstract: A computer-system includes a memory bus, a connector and a controller. The connector is configured to receive a memory module and prevent removal of the memory module from the connector in a first state. The connector allows removal of the memory module from the connector in a second state. The controller is configured to change a connection status between the connector and the memory bus in response to the connector changing from one of the states to the other state. A central processing unit of the computer system is configured to use the memory bus to store data in the memory module.

Abstract: An electronic system embodies a security system which provides varying levels of security based on the location of the system. As such, the system includes a location module, such as a geosynchronous positioning system (“GPS”) receiver that permits the system to determine its location relative to a plurality of preset location areas. Such location areas might be programmed to include the user's office, home, predetermined location for a business trip and the like. Based on the location area in which the system is located, the system invokes a security mode associated with that particular location area. Different location areas may have different security modes.

Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to a control logic in a memory controller, that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles, or may throttle down the operating speed of the memory devices, or may place some or all of the memory devices in a low power mode until conditions improve. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Abstract: A security system is provided which permits a user or owner of a portable electronic device to report the device missing to a security station. In response, the security station wirelessly transmits a security message or command to the portable electronic device which, in turn, responds by causing a “destructive” security action to occur. The destructive action may include erasing memory in the portable device, disabling certain functions (e.g., transmitting data, receiving data, accessing memory, etc.) or other types of actions such as reporting location information to the security station. Various security mechanisms can be implemented as well to minimize the risk that an unauthorized entity will be able to broadcast security messages to portable devices.

Abstract: A computer network employs a fault-tolerant or redundant switch architecture. The network includes redundant data paths coupling end nodes and switches. Fault-tolerant repeaters (FTRs) can be stand-alone devices or can be incorporated into the switches. Using error detection, the FTR checks to see if the data is good on all paths. If the data received on one path is “bad” and the data is “good” on another path, the FTR transmits the “good” data in place of the “bad” data. For any switch, a pair of incoming ports may be configured as redundant incoming ports and a pair of outgoing ports may be configured as redundant outgoing ports.

Abstract: An electronic device can automatically configure its communication capability depending on its location. The device preferably includes a location determination module which may comprise, for example, a GPS receiver. The location determination module provides a location value to a CPU which uses the location value to determine in which region of the world (e.g., a country) the device is located. Based on that determination, the device configures its communication capability to be compliant with the accepted communication protocols, carrier frequency, etc. of that region.

Abstract: A portable electronic device (e.g., a PDA) receives voice or other types of audio or even other types of media (e.g., video) and digitize, encrypt and transmit the voice stream to an external device (e.g., another portable electronic device) in real-time so that a real-time, two-way communication can occur. Each portable electronic device preferably includes a CPU executing security software to perform the encryption and decryption functions. The devices may communicate with each other via a standard telephone system or other type of communication media.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.

Abstract: A computer system includes multiple controllers that assist in executing the Power-On Self Test (POST) sequence to minimize the time required to complete system initialization. By shifting some of the responsibilities for executing the POST sequence to other controllers within the system, the testing and initialization of system devices can proceed concurrently. The controllers interface with peripheral devices, and include a register set that includes command information for initializing the testing and initialization of associated peripherals. The register set also includes dedicated bits for indicating the status of testing and initialization cycles, which can be read by the CPU to determine if testing or initialization is in progress, if it has completed, and if any errors have occurred. The register set also includes a configuration register for indicating configuration information and operating parameters of the initialized drive or peripheral.

Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to control logic in a memory controller that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices. In addition, the memory controller also monitors the expected remaining life of the memory devices, and the number of errors occurring in the memory devices, and based on these parameters, may change the frequency of the calibration cycles.

Abstract: A computer system having a main memory and a cache memory, the computer system uses portions of the cache memory to store information from defective main memory locations until the main memory can be repaired. The address space of the main memory is always maintained by substituting cache-lines of cache memory for the defective main memory locations. A fail-over memory status bit in the cache memory controller indicates when a cache line of the cache memory contains fail-over information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm. When the fail-over status bit is set, the contents of the fail-over memory location(s) remains in the cache-line and all memory reads and writes are directed to only that cache-line of the cache memory and not the main memory for the fail-over memory location(s).

Abstract: A method and system of intrachassis computer component command and control. The existing power rail is used as network connectivity. Further, the CEBus standard (or a CEBus standard modified for the particular power bus) is used to provide platform management functionality. This management functionality is similar to that provided by the proposed IPMI specification. However, the management functionality is implemented intrachassis, that is, it is applied to the internal components of the machine. Particularly advantageous functions, such as rollcall enumeration and command authentication and verification, are included in a preferred embodiment. Further, because these innovative techniques utilize the existing power rail, no additional external cables are required.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: A computer system with a plurality of peripheral busses is adapted to permit multicast signals to be transmitted by a device on one peripheral device to multiple devices on the other peripheral bus in a single bus cycle. In an exemplary embodiment, two PCI busses are provided, and master devices on either bus are capable of transmitting multicast signals to multiple targets on either bus. Targets of a multicast cycle are identified by a target identification signal on a first and a second multicast bus. A bus bridge relays the data for the multicast cycle between bridges. In an exemplary embodiment, a sideband signal from the master to the bridge indicates a multicast signal has been transmitted on the bus. In response, the bridge relays the multicast data to the other bus, while also transmitting a sideband signal to devices on the second bus indicating multicast data is being transmitted on that bus. Targets identified on that bus than capture the multicast data.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.