Abstract: A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligent storage devices and/or controllers, communications devices, video devices and audio devices. The I/O devices perform peer-to-peer message and data transfers, thereby bypassing the operating system running on the computer's CPU. The intelligent I/O devices encrypt messages and data before transmitting them on the I/O bus and conversely decrypt the messages and data upon reception. The encryption provides secrecy and/or authentication of the sender. The devices use keys or passwords to encrypt/decrypt the data. The keys are stored in non-volatile memory in the devices and are distributed to the devices by the system BIOS at initialization time.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as an interface bridge between a Fibre Channel Arbitrated Loop ("FC-AL") interface and the host and memory buses. The function of the multiple use chipset is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an FC-AL bridge interface is to be implemented. Selection of the type of bus bridge (AGP or FC-AL bridge interface) in the multiple use core logic chipset may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a FC-AL bridge interface device connected to the common AGP/ FC-AL bus. FC-AL information may be stored in the computer system main memory using the high speed FC-AL bridge interface.

Abstract: A method and apparatus for detecting insertion and removal of memory modules in a computer system using standard connectors is disclosed. A memory controller includes logic to read serial presence bits from memory modules incorporating such serial presence features. In response to system software the memory controller monitors a particular slot connector where a memory module is to be inserted or removed. Changes in the serial presence bits indicate insertion or removal. Each slot connector is further connectable to a memory bus for insertion and removal of memory modules while the computer system is operational.

Abstract: A method of theft protection for computers and computer related hardware. Warranty fraud, theft of proprietary technology, and hardware theft are minimized by encoding the hardware components such that a digitally authenticated handshake must be performed between the system and the component at power-up. If the handshake is successful, normal operation continues with all enhancements. If the handshake is unsuccessful, the device is disabled or shifted into a lower performance mode.

Abstract: Data errors on a communications channel in a computer system are corrected. The data is transmitted over the communications channel in a sequence of time-multiplexed phases. A storage device accumulates the phases of data. An error detector and correction device checks the accumulated data for a data error and corrects the data error. The error detection and correction device can correct a one-bit data error, a two-bit data error, and a three-bit data error. Multiple bit errors can be corrected if the multiple bits of data are transmitted over one cable wire in multiple time phases. The communications channel carries the data over N sub-channels, and a parity check generator employs a predetermined parity check matrix based upon the N sub-channels and a probability that multiple errors in the accumulated data are attributable to a faulty sub-channel that affects the same data position in different time phases of the data.

Abstract: A cache system for multiple processors including multiple caches, one of the caches serving each respective processor, a main memory system, and a bus interconnecting the caches and the main memory, the bus allowing data to be written directly between the caches without accessing the main memory system.

Abstract: A fault tolerant 64-bit data-width peripheral component interconnect (PCI) bus system in a computer system that may recover from a fault(s) occurring on either the upper or lower 32-bit portions of a 64-bit data-width PCI bus. When a parity error is detected on one of either the upper or lower 32-bit portions of the 64-bit data-width PCI bus, the 32-bit portion not having the parity error is used to transfer data and the one having the parity error is inhibited from further use. The PCI bus may be dynamically configured for transfer of data at 64-bits per clock, or at 32-bits per clock over either the upper or lower portions of the PCI bus. New signals SWAP# and SWAP.sub.-- ACK# are used to accomplish the fault tolerant operation. 64-bit disable and swap enable bits in a PCI device command register are used to disable 64-bit data transfer, and swap data transfer from the lower portion to the upper portion of the PCI bus, respectively.

Abstract: An improved system and method for FLASH BIOS upgrades which is particularly useful in network hubs. Each hub or node which is equipped with a FLASH memory is also equipped with a validation system, which ensures that a received FLASH upgrade is authorized and uncorrupted. Each set of instructions to be flashed is marked both with a vendor authorization digital signature and also a system administrator authorization digital signature, and BOTH digital signatures must be recognized by the validation system before the FLASH memory will be upgraded. Because digital signatures are used for security purposes, flash upgrades can be performed from any location on the network, and are not limited to an administrative node.

Abstract: A computer system having a CPU, a disk array system accessible by the CPU, and a disk array controller that includes error detection and connection logic. The disk array controller includes a processor and a memory system connected to signal lines carrying data bits, address bits, and check bits. An error detection and correction device is connected to detect and correct N-bit errors in the data bits using the check bits, N being greater than two. An error in the address bits is detected using the same check bits. The data bits are organized as multiple bytes, and the error detection and correction device is connected to detect and correct up to eight-bit errors in each byte and to detect a single-bit error or a two-adjacent-bit error in the address bits.

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium.RTM. Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry.

Abstract: A computer network system having a plurality of nodes, one of which is adapted as an administrator node, the administrator node for securely receiving code information from a code provider disposed external to the network system and for securely sending the code information to at least one of the nodes.

Abstract: A computer system incorporating a two-piece authentication procedure for securely providing user authentication over a network. In the disclosed embodiment of the invention, a user password is entered during a secure power-up procedure. The user password is encrypted by an external token or smart card that stores an encryption algorithm furnished with an encryption key that is unique or of limited production. A network password is thereby created. The network password is maintained in a secure memory space such as System Management Mode (SMM) memory. The network password is then encrypted and communicated over the network. The network password may be encrypted using the server's public key or another key that is known to the server. Optional node identification information is appended to the network password prior to communication over the network. Once received by the server, the encrypted network password is decrypted using the server's private key.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a remote peripheral component interconnect ("remote-PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and the remote-PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or a remote-PCI bus bridge is to be implemented. Selection of the type of bus bridge (AGP or remote-PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a remote-PCI device connected to the common AGP/remote-PCI bus.

Abstract: A memory system for performing error detection and correction including a memory device that stores a plurality of data words, where each data word has a plurality of data bits and at least one associated check bit. The memory system further includes memory control circuitry that reads a plurality of data words in multiple cycles to form a block word that includes a sufficient number of check bits to perform detection of double bit errors and correction of single bit errors. A 72-bit block word is formed by grouping smaller data words retrieved from the memory device. For a 9-bit device with eight data bits and one check bit, eight burst cycles may be used to retrieve a 72-bit data block. Similarly, for 18-bit devices, four burst cycles may be used to retrieve the data block and for 36-bit devices, two burst cycles may be used to retrieve the data block. The memory system further includes error logic that receives and performs error detection and correction upon the block word.

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of peripheral component interconnect ("PCI") buses capable of operating at 66 MHz. Each of the plurality of PCI buses have the same logical bus number. The core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device connected to the plurality of PCI physical buses. Each of the plurality of PCI buses has its own read and write queues to provide transaction concurrency of PCI devices on different ones of the plurality of PCI buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used.

Abstract: A programmable memory device including a register that stores a programmable mode select bit, a data input, a control input and decode circuitry that decodes the mode select bit to determine whether the memory device operates in either a check mode or a mask mode. The control input receives at least one control bit for each data byte received by the memory device during a write operation or cycle. The function of the control bit(s) depends upon the mode select bit. In a check mode of operation, each control bit functions as a parity/check bit for a corresponding data byte, where the memory device stores the check bit with its corresponding data byte during each write cycle. In the mask mode of operation, each control bit functions as a mask bit for a corresponding data byte, where the memory device selectively stores or masks the data byte depending upon the state of the corresponding mask bit.

Abstract: In a computer system having a receiving computer and a source computer, a method for the remote flashing of the BIOS in the receiving computer including the steps of transferring the flash information from the source computer to the receiving computer, with the flash information including the flash code, the flash code instructions and an encrypted digital signature corresponding to the flash code. The receiving computer is operably placed in a secure mode. A hash value corresponding to the flash information is calculated, and the hash value from the flash information is decrypted. The flash code is validated by comparing the decrypted hash value of the flash information to the calculated hash value, and if validated, the BIOS if flashed with the new flash code.

Abstract: In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.

Abstract: A method is described of detecting and correcting errors in a computer having a memory subsystem including a burst DRAM device. The method includes the steps of beginning a write operation of N data bits to the burst DRAM device, generating M check bits from the N data bits, writing the N data bits and the M check bits to the burst DRAM device, reading the N data bits and M check bits from the burst DRAM device, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct any single bit error within the N data bits and the M check bits and to detect any double bit error within the N data bits and the M check bits. A computer system is also described having a central processing unit and a memory subsystem.