Abstract: The present invention relates to a method of covalently attaching a chromosome within a cell to a matrix including modifying a plurality of nucleotides within the chromosome to include a matrix attachment moiety wherein the chromosome contacts the matrix, and attaching the matrix attachment moiety of the plurality of nucleotides to the matrix, thereby attaching the chromosome to the matrix.

Abstract: A heat sink with a first sub-area and a second sub-area, designed for contacting a large area of a printed circuit board populated with electronic components. A thermal isolation extends between the first sub-area and the second sub-area, and a rigid mechanical connection that spans the thermal isolation connects the first sub-area to the second sub-area. As a result, the heat sink allows an assignment of sub-areas to electronic components on the printed circuit board, and contributes to mechanical stabilization of the printed circuit board.

Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.

Abstract: The present invention relates to a method of covalently attaching a chromosome within a cell to a matrix including modifying a plurality of nucleotides within the chromosome to include a matrix attachment moiety wherein the chromosome contacts the matrix, and attaching the matrix attachment moiety of the plurality of nucleotides to the matrix, thereby attaching the chromosome to the matrix.

Abstract: A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Abstract: Disclosed herein are devices and methods for assessing the surface of a target cardiac tissue and for delivering a tissue anchor to cardiac tissue at a preselected depth within the myocardium in a beating heart procedure. In one variation, an anchor delivery device comprises an elongate body, a tissue anchor disposed within a first longitudinal lumen of the elongate body, and a tissue depth indicator slidable within a second longitudinal lumen of the elongate body. The tissue depth indicator has a first configuration that indicates the boundary of the surface of the target tissue and a second configuration that indicates when the distal tip of the elongate body has been advanced to a preselected depth into the target tissue. In some variations, a tissue depth indicator may also be configured to resist or limit the penetration of the delivery device into tissue after a preselected depth has been reached.

Abstract: The present invention relates to a process for hydroconversion of a heavy hydrocarbon feedstock in the presence of hydrogen, at least one supported solid catalyst and at least one dispersed solid catalyst obtained from at least one salt of a heteropolyanion combining molybdenum and at least one metal selected from cobalt and nickel in a Strandberg, Keggin, lacunary Keggin or substituted lacunary Keggin structure.

Abstract: A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metal interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor structure to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.

Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.

Abstract: A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Abstract: A semiconductor device includes a base structure including contacts and a first interlevel dielectric (ILD) layer, a metal-insulator metal (MIM) capacitor structure on the base structure, a second ILD layer on the MIM capacitor structure, and a plurality of vias penetrating through the first and second ILD layers to respective ones of the contacts.

Abstract: Systems and methods may be used to produce coated components. Exemplary semiconductor chamber components may include an aluminum alloy comprising nickel and may be characterized by a surface. The surface may include a corrosion resistant coating. The corrosion resistant coating may include a conformal layer and a non-metal layer. The conformal layer may extend about the semiconductor chamber component. The non-metal oxide layer may extend over a surface of the conformal layer. The non-metal oxide layer may be characterized by an amorphous microstructure having a hardness of from about 300 HV to about 10,000 HV. The non-metal oxide layer may also be characterized by an sp2 to sp3 hybridization ratio of from about 0.01 to about 0.5 and a hydrogen content of from about 1 wt. % to about 35 wt. %.

Abstract: In a semiconductor device being fabricated, a gate structure, a first source/drain (S/D) structure, and a second S/D structure are formed. A first spacer of a first dielectric material is formed between the gate structure and the first S/D structure. A second spacer is formed between the gate structure and the second S/D structure, such that a first gap is created within a second dielectric material of the second spacer.

Abstract: A computer-implemented document management method is discussed. The method includes displaying in a messaging application a plurality of folders for storing electronic mail messages, analyzing content one or more of the electronic mail messages to locate identifiers associated with matters in a document management system, and generating a user-selectable object that, when selected, automatically causes the generation of a document management display for a user of the messaging application.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include a substrate including a central portion and a pair of outer portions. A first self-assembled monolayer is attached to the central portion of the substrate. A second self-assembled monolayer is attached to the first self-assembled monolayer. A first dielectric layer is disposed on each of the outer portions. A second dielectric layer is disposed on the first dielectric layer.

Abstract: A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Abstract: Described herein are devices and methods for delivering implants that include multiple coupled anchors. The anchors are secured to tissue using a multi-opening guide tunnel that is configured to releasably retain one or more portions of the implant located between two of the anchors. The releasable retention of one or more intervening portions of the implant maintains the position of the implant and the guide tunnel until the implant is secured to the tissue. The multi-opening guide tunnel permits securement of the multiple anchors without requiring repositioning of the guide tunnel for each anchor.

Abstract: A method for fabricating a semiconductor device includes forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar, and depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry.

Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.

Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.