Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Abstract: An implantable prosthetic valve, according to one embodiment, comprises a frame, a leaflet structure, and a skirt member. The frame can have a plurality of axial struts interconnected by a plurality of circumferential struts. The leaflet structure comprises a plurality of leaflets (e.g., three leaflets arrange to form a tricuspid valve). The leaflet structure has a scalloped lower edge portion secured to the frame. The skirt member can be disposed between the leaflet structure and the frame.

Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

Abstract: A two-part implantable heart valve and procedure are disclosed that allow expansion and positioning of a first part of the implantable heart valve having a temporary or transient valvular structure. A second part of the implantable heart valve is deployed within the first part and attaches thereto. The valvular structure of the second part then acts to function as the heart valve replacement. A tool or system is provided for determining an adequate percutaneous heart valve size for a given stenotic valve. A balloon can be inflated inside the stenotic valve to a desired pressure. When this pressure is reached an angiographic image is taken and the balloon diameter is measured at a waist area created by contact between the balloon and the stenotic valve. The diameter represents the minimum percutaneous heart valve diameter to be implanted.

Abstract: A prosthetic mitral valve assembly and method of inserting the same is disclosed. In certain disclosed embodiments, the prosthetic mitral valve assembly has a flared upper end and a tapered portion to fit the contours of the native mitral valve. The prosthetic mitral valve assembly can include a stent or outer support frame with a valve mounted therein, The assembly can be adapted to expand radially outwardly and into contact with the native tissue to create a pressure fit. One embodiment of a method includes positioning the mitral valve assembly below the annulus such that the annulus itself can restrict the assembly from moving in an upward direction towards the left atrium. The mitral valve assembly is also positioned so that the leaflets of the mitral valve hold the assembly to prevent downward movement of the assembly towards the left ventricle.

Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

Abstract: A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Abstract: Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.

Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

Abstract: A semiconductor device having a capacitor containing an insulator material having a high dielectric constant and high charge storing capability of the following formula: (A.sup.1).sub.x (A.sup.2).sub.2-x (D).sub.d (B.sup.1).sub.y (B.sup.2).sub.1-y O.sub.4 where A.sup.1 and A.sup.2 are cations, B.sup.1 and B.sup.2 are anions, 0.ltoreq.x.ltoreq.2 with the proviso that A.sup.1 and A.sup.2 are different types of atoms when 0<x<2, and 0.ltoreq.y.ltoreq.1 with the proviso that B.sup.1 and B.sup.2 are different types of atoms when 0<y<1, and D is an optional dopant in a total amount of 0.ltoreq.d.ltoreq.0.1.

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips.

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) followed by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips.

Abstract: Disclosed is a process for depositing a conformal polymer coating on selected areas of a silicon substrate. The substrate is first exposed through a mask to a gaseous plasma so as to form a film of desired pattern, the plasma comprising a compound having strong electron donating characteristics. Then, the patterned film and the remaining substrate not covered by the film are exposed to the vapor of a monomer, which condenses and polymerizes on the exposed substrate surfaces, but not on the film. The film serves to inhibit substantial deposition of the coating, so as to provide a selective deposition, where the coating is formed only on those areas of the substrate where desired.

Abstract: Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line.

Abstract: Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element.

Abstract: Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.