Patents by Inventor Son V. Nguyen

Son V. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5539154
    Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon
  • Patent number: 5536360
    Abstract: The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, David M. Dobuzinsky
  • Patent number: 5468687
    Abstract: A method for low temperature annealing (oxidation) of high dielectric constant Ta.sub.2 O.sub.5 thin films uses an ozone enhanced plasma. The films produced are especially applicable to 64 and 256 Mbit DRAM applications. The ozone enhanced plasma annealing process for thin film Ta.sub.2 O.sub.5 reduces the processing temperature to 400.degree. C. and achieves comparable film quality, making the Ta.sub.2 O.sub.5 films more suitable for Ultra-Large Scale Integration (ULSI) applications (storage dielectric for 64 and 256 Megabit DRAMs with stack capacitor structures, etc.) or others that require low temperature processing. This low temperature process is extendable to other high dc and piezoelectric thin films which may have many other applications.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: November 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Dan Carl, David M. Dobuzinsky, Son V. Nguyen, Tue Nguyen
  • Patent number: 5462812
    Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: October 31, 1995
    Inventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon
  • Patent number: 5455204
    Abstract: The invention provides a continuous rapid thermal process for forming a substantially uniform oxynitride film on fingered three-dimensional silicon structures comprising cleaning of the silicon substrate and growth of silicon oxide in the presence of ozone, nitridation of the silicon oxide layer in the presence of NH.sub.3 and reoxidation of the oxynitride layer in the presence of oxygen.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: October 3, 1995
    Assignee: International Business Machines Corporation
    Inventors: David M. Dobuzinsky, Son V. Nguyen, Tue Nguyen
  • Patent number: 5412246
    Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG..
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: May 2, 1995
    Assignee: International Business Machines Corporation
    Inventors: David M. Dobuzinsky, David L. Harmon, Srinandan R. Kasi, Donald M. Kenney, Son V. Nguyen, Tue Nguyen, Pai-Hung Pan
  • Patent number: 5217567
    Abstract: Disclosed is a process for etching a film of boron nitride with high selectivity to a layer of silicon dioxide or silicon nitride. The process involves exposing the film to a plasma formed from a mixture of an oxygen-containing gas, such as oxygen, and a small amount of a fluorine-containing gas, such as CF.sub.4. The process provides a high etch rate and anisotropic profiles, as well as good uniformity.
    Type: Grant
    Filed: February 27, 1992
    Date of Patent: June 8, 1993
    Assignee: International Business Machines Corporation
    Inventors: Donna R. Cote, David M. Dobuzinsky, Son V. Nguyen
  • Patent number: 5204138
    Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.
    Type: Grant
    Filed: December 24, 1991
    Date of Patent: April 20, 1993
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, David M. Dobuzinsky, Douglas J. Dopp, David L. Harmon
  • Patent number: 4811067
    Abstract: A dynamic random access memory is provided wherein each cell has a storage capacitor and switching device and a bit/sense line or plate located along a sidewall of a trench formed in a semiconductor substrate. In a more particular structure of the cell, the trench width defines the length of the switching device, with the storage capacitor and a highly conductive bit/sense line being formed along opposite sidewalls of the trench. In an array of such cells, the highly conductive bit/sense line or plane interconnecting a large number of the cells of the array extends continuously from cell to cell within the trench at a sidewall thereof. Likewise, the storage capacitors of these many cells have a highly conductive common plate extending continuously within the trench at the opposite sidewall.
    Type: Grant
    Filed: May 2, 1986
    Date of Patent: March 7, 1989
    Assignee: International Business Machines Corporation
    Inventors: Brian F. Fitzgerald, Kim Y. T. Nguyen, Son V. Nguyen
  • Patent number: 4635139
    Abstract: A glide head is used to test a rigid magnetic disk surface for projecting asperities. Using a two rail head with the read/write transducer mounted at the rear of the rail at the side of the head toward which the head is being radially advanced and skewing the head so that the trailing edge of the head approaches each track before the leading edge as the head is advanced, it is possible to write a pattern from a known position relative an event or asperity identified by a mechanical transducer associated with the head to the index location. Using a developer, it is then possible to readily identify the asperity during microscopic examination of the disk surface.
    Type: Grant
    Filed: August 26, 1985
    Date of Patent: January 6, 1987
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, James M. Severson